Atomic Layer Deposition (ALD) has become a foundational technology in the semiconductor industry, enabling the precise, conformal deposition of ultra thin films essential for advanced logic, memory, power, RF and photonic devices. As device dimensions shrink and architectures become more complex, the control of atomic-level impurities prior and during ALD processes has emerged as a critical determinant of device performance, yield and long-term reliability [1] [2]. Even very low contamination levels of carbon and metallic residues together with uncontrolled incorporation of hydrogen and oxygen on the surface  can introduce interface defect states and mid-gap traps, increase leakage current, degrade the ALD film adhesion and ultimately reduce device manufacturing yield, reliability and performance [1]. The industry’s relentless drive toward device miniaturization and increased component density has placed unparalleled demands on thin film quality and interface engineering, making atomic-level cleanliness not just a process optimization, but a fundamental enabler for the next generation of electronic, photonic and sensing devices [1].

Despite the inherent advantages of ALD—such as excellent step coverage and atomic-scale thickness control—persistent challenges related to interface contamination, defect generation and uncontrolled oxidation threaten to undermine the full potential of this technology. In this context, SisuSemi’s atomic-level solution for removing contaminants and defects stands out as a transformative and enabling approach, directly addressing the most pressing reliability and performance bottlenecks in ALD-enabled device manufacturing. This is the focus of the white paper.

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Leakage currents, defects & why they matter

In modern semiconductor devices, power dissipation has two large components:

• Dynamic (switching) power: consumed when transistors switch, charging/discharging capacitances, etc.
• Static or leakage power: consumed even when transistors are idle/off due to sub-threshold leakage, gate oxide leakage, junction leakage, etc.

As transistors scale down (5nm, 3nm, etc.), physical dimensions shrink, voltage margins compress, gate oxides become thinner, higher fields appear. All this exacerbates leakage issues. But in addition to the usual scaling-driven leakages, atomic-level defects, contamination, and surface/interface flaws introduce localized states, trap levels, unwanted charge paths or enhanced leakage at edges or perimeters of devices. These degrade switching thresholds, reduce carrier mobility, degrade control over off-state leakage — hence increasing static power.

Recent studies have explicitly shown the impact of such defects. For example, Semiconductor Engineering recently commented that atomic-level defects and contamination are “hidden but powerful driver(s)” of power consumption in data centers, via mechanisms like increased leakage currents, reduced switching efficiency, and degraded carrier mobility. Likewise, in GaN substrates, work on threading dislocations has shown that screw and mixed dislocations act as leakage paths under reverse bias.

In edge devices, where duty cycles may include long standby periods, static leakage becomes a larger fraction of total power. A milliwatt or microamp extra leakage per transistor, multiplied by many transistors, can drain batteries faster than expected.

AI inference & power efficiency

AI workloads (even inference) generally require higher switching activity, more complex architectures (accelerators, specialized memory, vector units, etc.) and more persistent idle states. Some strategies help:

• Quantization, pruning, model compression, hardware accelerators that lower switching energy.
• Better sleep / duty cycling to minimize active time. TinyVers, for example, shows very low power consumption in continuous operation and even lower in deep-sleep or wake-up modes.
• Using more efficient microcontrollers or AI-optimized SoCs: in comparative studies, newer cores with better vector instruction sets and optimized cache architectures have significantly better energy per inference than older ones.

But none of these approaches can fully compensate if the base static/leakage currents are high due to defects or contamination.

Why surface cleanliness & atomic-level defect control become key

This is where technologies like those offered by SisuSemi matter. To get down to very low leakage and reliable behavior in ultra-low power standby or always-on modes, a chip must have:

• Clean surfaces/interfaces, with minimal contamination (metals, residues) that can act as trap / recombination centers or leakage paths (e.g. metal contamination in pMOS devices correlates with higher off-state leakage)
• Minimal atomic‐scale defects: dislocations, vacancies, interface states, surface roughness. Studies indicate that e.g. screw dislocations in GaN, or surface damage at the perimeters, significantly increase reverse leakage currents.
• Process optimizations: annealing, oxidation / oxide interface control, ultra-clean environment, gettering, careful edge / perimeter definition. All to reduce trap densities, passivate defect states, and avoid unintended leakage.

SisuSemi’s UHV surface cleaning, atomic-level defect mitigation, and low contamination process steps can help reduce leakage currents, enabling better battery life, lower standby power, higher reliability — all essential for edge AI devices.

Implications for design, manufacturing & ROI

• Design side: Edge AI chips will need to budget not just for dynamic/inference power but also for static power leakage. Designs that ignore leakage have a risk that battery life is not optimized.
• Manufacturing / process control: fabs will need tighter controls on surface contamination and defect levels especially at interfaces and perimeters; cleaning steps (before critical depositions, before overlay, etc.) become more critical.
• Metrology and QA: detecting and quantifying atomic‐scale defects, surface residues, interface trap densities, etc., becomes necessary to ensure yield and low leakage.
• ROI: While more stringent cleaning, UHV methods and defect mitigation may increase cost, they may more than pay off via longer battery life, fewer warranty returns, better device reliability and competitive differentiation in power-sensitive markets.

Conclusion

As AI pushes outward from the cloud into edge devices and battery-powered IoT nodes, every micro‐watt counts. Dynamic power optimizations are well known, but static or leakage power becomes disproportionately important at low activity or in ultra-constrained power settings. Atomic-level defects and contamination are not minor nuisances — they directly undermine leakage current, threshold stability and device efficiency. Technologies that can clean, passivate, control surfaces and defects at the atomic scale — such as what SisuSemi offers — are going to be increasingly critical components in the semiconductor roadmap for edge AI.

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Water consumption in fabrication

Semiconductor fabrication demands extremely clean conditions: contamination—even at atomic scales—can trigger defects in devices, reduce performance, and ultimately drive up ultrapure water (UPW) usage. Here’s how:

1. Surface reactivity and cleaning burden

Surface defects—vacancies, dislocations, native-oxide roughness—create highly reactive sites that strongly attract contaminants: ions, organics, particulates. Removing them requires aggressive cleaning chemistries (e.g., SC-1, SC-2, HF dips) followed by multiple UPW rinses. Each extra rinse can consume thousands of liters per wafer, rapidly scaling across a fab.

2. Contamination, yield loss and rework loops

Even trace metal or organic contaminants, lodged in surface defects, can cause electrical failures or stiction faults. A drop in yield—from, say, 95% to 90%—could mean hundreds of thousands of dollars lost per batch, and additional water-intensive reprocessing cycles. Quality control cleaning loops further compound UPW consumption.

3. UPW volume magnitude

Typical fabs consume 7–35 million liters of UPW per day, equivalent to a small city’s usage. Producing UPW is itself inefficient: around 1,400–1,600 liters of municipal water are needed to make 1,000 liters of UPW.

4. Sustainability and environmental pressure

As demand for chips surges, so does water stress. TSMC’s Phoenix facility plans to reclaim ~65% of water used, and Intel is pursuing net-positive water use by 2030, including desalination and recycling strategies.

Ripple effects: From chip quality to economics and sustainability

Chip performance & quality

Atomic-scale contaminants may form “killer defects” in logic circuits. For example, a ~20 nm particle on a 100 nm feature could cause catastrophic device failure. Such defects not only lower performance but may induce failure modes like leakage or reduced reliability.

Manufacturing yield

Yield is aggressively tied to defect density: TSMC reported ~80% average yield on 5 nm test chips (~17.9 mm² dies), but yield plummets to 32% when die size increases to 100 mm². Smaller features and larger dies demand even stricter contamination control.

Economics

A modest yield drop is costly. Saying again: going from 95% to 90% can shift an entire production run from profitable to unprofitable, costing hundreds of thousands in wasted labor, machine time, and materials. Moreover, each rework round multiplies UPW consumption and energy use.

Sustainability

Beyond water, contamination control—and its failures—escalate wastewater treatment needs, chemical usage, and energy. Globally, Taiwanese electronics manufacturers increased water use ~6.1% per year from 2015–2020, tracking with production volume increases. If unchecked, this growth locks in escalating environmental burdens.

How reducing defects and contamination pays dividends

Mitigating atomic‑level surface defects and contamination, with advanced process control and physical defect removal solutions, delivers cascading advantages:

1. Cutting UPW consumption

With fewer contaminants to clear, fabs can trim cleaning steps. A well-designed water management plan—segregating rinse waters, recycling lightly contaminated flows, and redirecting them to UPW makeup—can reduce water use by up to 90%.

2. Elevating performance & quality

Cleaner surfaces lower “killer defect” incidence. Maintaining UPW purity—particles <10 nm, TOC <1 ppb, metals/ions <1–10 ng/L—ensures that lithography and etching yield consistent, reliable patterns.

3. Boosting yield

With contamination minimized, yield grows. Fewer failed chips mean more sellable output per wafer, enhancing cost efficiency. Smaller die geometries benefit most, where contamination margin of error is wafer-thin.

4. Strengthening economics

Better yield and fewer reworks translate to lower per-chip costs. Savings in water, chemicals, energy, labor, and equipment utilization further compound gains. A fab operating smoothly with high yield and minimal reprocessing is far more profitable.

5. Advancing sustainability

Less water use, fewer chemicals, and lower wastewater generation improve environmental impact. Many fabs now target water recycling/reuse: TSMC Phoenix aims for 65% reclaimed water; Intel targets net-positive usage by 2030; Micron looks to conserve 75% via reuse and restoration.

Real-world examples

Final thoughts: A strategic call to action

Addressing atomic-level defects and contamination is not just a tech imperative—it’s a strategic opportunity. By investing in meticulous surface engineering, advanced monitoring (e.g., real-time liquid contamination systems) and smart water-reuse strategies, fabs can:

• Sharply cut ultrapure water use and production costs
• Enhance chip quality and maximize yield
• Boost profitability through reduced rework and higher throughput
• Deliver on sustainability goals, positioning as operational leaders and environmental lighthouses

SisuSemi’s surface engineering solutions are designed to meet these exact challenges – reducing atomic-level defects, minimizing water consumption, and enabling fabs to operate with greater efficiency and environmental responsibility.

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