Roadmaps are the least hyped documents in the semiconductor industry, which is exactly what makes them worth reading closely. Nobody is trying to raise money off a roadmap. They’re written by research consortia and standards bodies for an audience of engineers who will hold the authors to every claim, which makes them a rare source of unvarnished signal in a field otherwise full of press releases. Read enough of them, in sequence, and a pattern emerges that’s easy to miss in any single document: the industry’s own technical roadmaps are quietly describing a bottleneck that has nothing to do with lithography, and everything to do with what happens at the interface between materials.

Where the device roadmap is heading

Imec’s published logic technology roadmap traces a clear trajectory: from today’s gate-all-around and nanosheet transistors, toward complementary FET (CFET) architectures that stack n- and p-type devices vertically to shrink cell footprint, and eventually toward two-dimensional channel materials — atomically thin layers such as tungsten disulfide and molybdenum disulfide — as the industry pushes toward sub-1nm gate lengths. Imec’s own researchers have been explicit about why: as devices shrink, conventional silicon channels run into short-channel effects that limit further scaling, and 2D materials offer a way around that limit precisely because they can be structured down to a single atomic layer.

That’s a genuinely exciting architectural roadmap. It’s also a roadmap that runs directly into a materials problem before it runs into anything else. In imec’s published work on integrating 2D materials into the logic roadmap, the organization is direct about where the biggest obstacle sits: channel material quality and control of defectivity are described as the single largest challenge to improving device performance in these architectures, ahead of contact resistance and ahead of the modeling work still needed to design around them. That’s not a minor thing. It’s the industry’s own research arm naming interface and surface quality as the pacing item for the next generation of transistor architecture — not lithography, not even the device physics itself.

The lithography side of the roadmap tells a compatible story. As imec and its partners push toward High-NA EUV to keep pace with shrinking pitches, the organization has flagged stochastic defectivity — essentially, statistically unavoidable pattern defects that emerge at these dimensions — as an active area of investigation in its own right, not a solved problem being carried forward from prior nodes.

The yield-enhancement chapter says the quiet part out loud

If imec’s device roadmap identifies the problem, the IEEE’s International Roadmap for Devices and Systems (IRDS) shows how deeply it’s already embedded in industry planning. IRDS maintains a standing Yield Enhancement chapter, built specifically around defect prevention and what the roadmap calls proactive contamination control — and it treats this as a cross-cutting concern touching front-end process technology, interconnect processing, lithography, metrology and process integration simultaneously. That’s an unusually wide impact for a single roadmap chapter, and it reflects a simple physical reality: a contamination or defect problem at the interface doesn’t stay contained to one process step. It propagates through everything built on top of it.

The IRDS roadmap makes another point worth noting: as critical dimensions shrink, the size of a defect that can actually break a device shrinks right along with it, while the industry’s ability to detect and characterize defects at that scale becomes proportionally harder. In other words, the tolerance for contamination is tightening at the same time the tools for finding it are straining to keep up. That’s precisely the kind of asymmetry that turns a manageable engineering problem into a structural bottleneck if it isn’t addressed directly.

Reading the two roadmaps together

Put imec’s device architecture roadmap next to IRDS’s yield enhancement chapter, and the shape of the next bottleneck becomes hard to miss. The device roadmap is moving toward architectures — stacked CFETs, atomically thin 2D channels — that have vanishingly little tolerance for surface and interface defects by design; there’s simply less material, and less margin, for a contaminant or an imperfectly ordered interface to hide in. The yield roadmap, meanwhile, is telling the industry that contamination control and defect characterization are already a standing, cross-functional concern at today’s dimensions, well before the field fully arrives at the architectures the device roadmap describes.

This isn’t a speculative reading. It’s the clear implication of putting two of the industry’s own consensus documents side by side. The interesting question isn’t whether atomic-scale interface quality becomes a binding constraint — the roadmaps already describe it as one. The interesting question is which approaches actually solve it, as opposed to managing around it with incrementally better versions of particle-level cleaning that was designed for a previous generation of device architecture.

It’s also worth noting what these roadmaps don’t say. Neither imec’s device roadmap nor the IRDS yield chapter prescribes a specific fix — that’s not what roadmaps are for. They describe the requirement and leave the solution space open, which is exactly why this is a useful area for investors and technical partners to watch closely: the industry has told everyone, in public, precisely which problem is worth solving next. What it hasn’t handed anyone is the answer.

Where this leaves companies working at that layer

This is the layer SisuSemi works in. Our ALP™ platform is built around exactly the problem the roadmaps above describe from two different directions: atomic-level ordering and contamination at semiconductor interfaces, in a form that’s compatible with the device architectures the industry is already committed to building. We didn’t arrive at this problem by reading roadmaps after the fact — we’d note that the roadmaps are simply confirming, in their own language, a bottleneck that shaped our research agenda well before this generation of documents was published.

For anyone doing diligence on a company in this space, the roadmaps are worth reading directly rather than taking any single company’s framing of them on faith. They’re public, they’re unusually candid about where the industry’s own experts think the hard problems sit, and — read carefully — they tend to be more convincing than any pitch deck built on top of them.

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