For decades, semiconductor manufacturing progress was described mainly through lithography, transistor dimensions and wafer-scale yield. The research papers reviewed here show that the industry’s attention is now moving deeper—toward individual interfaces, atomic residues, fixed charges, trapped ions, subsurface contamination and even fractions of a monolayer. 

That shift matters to investors and semiconductor professionals because it is not being driven only by university laboratories. Also, engineers from such semiconductor manufacturers like GlobalFoundries, Intel, Samsung Electronics, Micron, Infineon and Nexperia, as well as semiconductor-equipment specialists DISCO and Plasma-Therm, are heavily involved in the research.  

In other words, atomic-level defects and contamination are no longer merely interesting research topics. They are increasingly treated as manufacturing, yield, reliability and product-performance problems by companies that operate fabs, develop memory and logic technologies, build quantum devices and supply production equipment. 

Why scaling turns small imperfections into large business problems 

As semiconductor dimensions shrink, a contaminant atom or electrically active interface defect occupies a larger relative share of the functional structure. 

A Samsung–KAIST paper states directly that sub-20-nanometre integration requires atomic-scale control because infinitesimal elements can profoundly influence device characteristics. The authors identify residual oxide as a major component of interface defects and describe native-oxide removal before polycrystalline-silicon contact or epitaxial growth as a critical technology for DRAM, flash and logic devices. 

The same principle appears in Intel’s 2024 Nature paper. Intel researchers found that single-electron voltage variation could arise from charge defects such as interface traps or fixed charge in the oxide, together with oxide-thickness variation, line-edge roughness and work-function variation. They concluded that further reductions in fixed charge in the high-k stack could improve device behaviour. 

This is especially revealing. When devices are operated at the level of individual electrons, atomic-scale disorder becomes directly visible as a manufacturability and scaling constraint. Intel’s optimized process ultimately achieved 100% gate yield and 99.8% quantum-dot yield, demonstrating how controlling materials, charge and process variation can translate into wafer-level manufacturing results. 

Production-oriented research connects atoms to economics 

The strongest validation is that these studies connect microscopic surface and interface phenomena to measurable fab outcomes. 

A GlobalFoundries’ 2024 paper investigated wafer-edge yield loss in a 0.13-micrometre BiCMOS process. The study linked the RCA cleaning sequence, HF-last immersion and surface chemistry to particle generation, interface degradation, leakage and shorts. 

By removing the SC2 step and shortening HF-last immersion, GlobalFoundries reported a 50–75% reduction in low-edge-yield fallouts, a 79% increase in wafers achieving at least 90% edge yield and a 20.5% tightening of edge-yield variation. 

The lesson is important: even a mature and widely used cleaning sequence can create subtle surface interactions that translate into major production economics. GlobalFoundries concluded that process development must consider not only particle removal but also surface chemistry before sensitive downstream steps such as thin-gate-oxide formation, polysilicon deposition and epitaxial growth. 

Micron reaches a similar conclusion in high-volume DRAM manufacturing. Micron engineers describe defects and line-width roughness as major yield detractors in advanced bitline etching. Their treatment removed chloride residue, strengthened the chamber’s silicon-oxide coating, improved surface roughness by 30% and produced a 0.15% yield gain. 

In a mature memory fab, even a fraction of a percentage point in yield can have considerable commercial value. The Micron paper also warns that some defects can evade inline inspection and electrical probing, only to appear later as customer returns. 

Samsung’s research shows sustained industrial attention 

Samsung’s work provides perhaps the clearest evidence that this is a sustained industrial research priority rather than an isolated topic. Samsung has done a lot of investigations into ionic impurities, residues, interface traps, oxide defects and structural reliability. 

In a published paper Samsung’s DRAM Yield Enhancement and Memory Diffusion Technology teams explain that chlorine and hydrogen introduced during shallow-trench-isolation processing can act as traps and negatively affect DRAM structures. 

Their revised Trench-Ox process reduced interface-trap density, cut tRDL failures by 86%, increased data-retention time by 16% and dramatically reduced single-bit failures after packaging and module processing. Significantly, the process improved two DRAM characteristics normally considered to involve a trade-off. 

A second Samsung paper shows how residues can remain not only on the wafer surface but inside the silicon substrate. Replacing argon with oxygen during dechucking reduced surface chlorine and bromine anions by 93% and 50%, respectively, and reduced these contaminants by one to two orders of magnitude within the substrate. The treatment also reduced the damaged silicon layer and lowered interface-trap density. 

A third paper reports that fluorocarbon residue can survive etching, react during subsequent HF cleaning and form sub-micron particles that reduce manufacturing yield. Nitrogen treatment reduced surface fluorine by 79%, subsurface fluorine by 44% and completely suppressed the observed particle formation. 

The research also found that equipment humidity affects residue behaviour. This demonstrates that contamination control is not a single-step problem: it is an integration problem spanning chemistry, chamber condition, queue time, post-treatment and environmental control. 

Samsung’s 2024 paper produced with Sungkyunkwan University extends the issue from chemical contamination to nanoscale structural defects. The researchers examined shallow-trench-isolation seams that disturbed gate-oxide growth. Their spacer-STI solution increased seam depth by 40%, reduced the seam-area index to zero, increased gate-oxide thickness by 12% and improved breakdown reliability without changing the intended electrical characteristics of the high-k/metal-gate device. 

Cleaning can itself become a source of contamination 

One of the most commercially relevant messages is that contamination does not arise only from obviously “dirty” manufacturing steps. Cleaning and etching processes themselves can introduce or redistribute impurities. 

Infineon’s paper found carbon concentrations of 4.0% after phosphoric-acid nitride etching, 6.0% after buffered-oxide etching and 1.7% after SC1 cleaning. The authors detected organic compounds in the process chemistry and concluded that impurities could be adsorbed or incorporated into silicon during oxide etching. 

The paper links carbon contamination to hydrophobic surfaces, altered oxide growth, dielectric-thickness variation, spurious doping and reduced electrical functionality. Its figures also show incomplete etching and describe carbon incorporated inside the SiOx layer—not merely deposited on top of it—as a cause of electrical drift. 

The earlier Samsung–KAIST dry-cleaning study adds an atomic-scale mechanism. It found that residual fluorine can initiate local native-oxide regrowth and attract moisture or organic material. Surface analysis showed a strong relationship between residual fluorine and reoxidation beginning at Si–F defect sites. 

The key point is not that wet or dry cleaning is inherently superior. It is that every cleaning method changes the atomic termination and chemical reactivity of the surface—and those changes must be understood and controlled. 

The concern also extends beyond front-end transistor fabrication. DISCO and Plasma-Therm reported that plasma dicing generates fluorinated polymer residues on silicon sidewalls and beneath topographical overhangs such as solder balls and microbumps. Some of these areas cannot be reached by in-chamber post-treatment. 

Atomic and molecular contamination control will therefore also matter in advanced packaging, where narrower streets, smaller features and heterogeneous interfaces create new and increasingly inaccessible surfaces. 

What this validates—and what it does not 

The collective evidence presented above validates the importance and urgency of the problem space. Major semiconductor companies are publishing on interface traps, residual oxides, fixed charge, halogens, carbon, fluorocarbon polymers, damaged silicon and nanoscale structural defects because these phenomena affect yield, leakage, variation, data retention, breakdown reliability and customer returns. 

These papers do not, by themselves, validate SisuSemi’s Atomic-Level Purification technology or prove that one solution can address every defect mechanism. They validate the market need, the scientific rationale and the willingness of industrial R&D organizations to invest resources in atomic-level surface and interface control. SisuSemi is in the process of validating application-specific performance, process-integration compatibility, throughput, repeatability and cost of ownership with multiple industry players. 

For investors, that distinction is positive rather than limiting. The papers show that SisuSemi is not trying to create awareness around an invented problem. It is entering a field where leading manufacturers already measure, model and modify atomic-scale contamination because the economic consequences are visible at wafer, device and product level. The discussion above also shows that there is room for technologies capable of delivering repeatable purification and interface conditioning across several process contexts. 

The semiconductor industry’s next gains will not come only from printing smaller features. They will also come from controlling what remains on, beneath and between those features. The scientific community is paying close attention—and, crucially, much of that scientific community is working inside the world’s leading semiconductor companies. 

Contact us to learn more