ALP™ (Atomic Level Purification) is a semiconductor interface engineering methodology designed to restore atomic lattice order, reduce carbon and hydrogen contamination, and suppress interface trap density (Dit) at advanced 2 nm and 3 nm technology nodes and beyond.

In this blog we go deeper why this is needed, and what are the reasons why this really matters.

The clean‑surface foundation for 3 nm performance, power, and yield

Transistor scaling hasn’t stopped – it is confronting a new boundary: the atomic wall, where yield loss and leakage are increasingly driven by atomic-scale interface defects rather than geometry.


At 3 nm and below, device behaviour is no longer governed primarily by geometry. It is governed by surface physics.

 When channels are only a few dozen atomic layers thick, even minimal interface trap density (Dit), residual carbon species, hydrogen-related defects, or lattice disorder can measurably increase leakage, raise static power, and reduce yield.

At 2 nm and 3 nm nodes, horizontal nanosheet GAA transistors dramatically increase the surface-to-volume ratio of the channel, and because the gate surrounds the channel on all sides, interface trap states and surface defects now directly influence leakage and variability – a phenomenon increasingly documented in reliability studies of GAA nanosheet devices.

What once could be compensated by design margins is now a first-order device limiter.

Yet the industry’s process toolkit remains largely focused on particle removal and deposition precision. Wet cleans and plasma treatments remove residues, but they do not restore atomic lattice order, eliminate deeply embedded contamination, or suppress interface trap formation at its origin. As geometries shrink further, these residual atomic-level contamination increasingly dictate performance and yield.

ALP™ (Atomic Level Purification) addresses this structural gap. It is not incremental cleaning – it is a physics-level reset of the silicon surface before critical process steps.

By targeting interface defects and atomic contamination at their source, ALP™ establishes a low-defect baseline that reduces leakage, stabilizes variability, and enables downstream modules to perform at their intended limits.

At sub-3 nm nodes, Atomic Level Purification is no longer optimization. It is a prerequisite for continued scaling.

Why surfaces became the bottleneck

  • Moving from 3 nm to 2 nm in GAA designs drives contacted‑gate and metal pitches even tighter, which amplifies electrostatic sensitivity, line‑edge variability, and overall device‑to‑device spread.
  • As dimensions shrink, leakage rises sharply. Subthreshold leakage, gate‑oxide tunnelling, and defect‑assisted conduction become dominant mechanisms at these scales; interface states at the Si/oxide boundary are among the primary contributors.
  • Although the industry shifted from FinFET → GAAFET to improve electrostatic control and suppress leakage, the surface and interface quality now determine a disproportionate share of performance and yield at advanced nodes. Far more than geometry alone.

As scaling pushes into the sub‑3 nm era, where contacted gate pitch and metal pitch approach physical limits, improving atomic‑level surface and interface quality has become one of the highest‑leverage ways left to recover performance, power efficiency, and yield.

What is ALP™ (Atomic Level Purification)?

ALP™ introduces a new category: atomic-level interface engineering. It enables industry to take atomic-level surface control.

It is a patented solution that uses ultra‑high‑vacuum, temperature‑controlled surface purification and stabilization sequence that prepares silicon for the most demanding stages of advanced‑node manufacturing.

It is designed to address the atomic‑level contamination and defect mechanisms that conventional cleaning and plasma steps cannot fix without introducing damage.

What ALP™ delivers :

  1. Removes atomic‑scale contamination
    Eliminates stubborn residues and impurity species, such as carbon and hydrogen‑related fragments, that wet cleans and plasma treatments struggle to remove cleanly, especially without damaging the silicon surface.
  2. Repairs and orders the near‑surface lattice
    Restores crystalline order in the top atomic layers, suppressing defect‑mediated leakage paths and reducing interface‑trap density (Dit), which is crucial for leakage and variability control at advanced pitches.
  3. Passivates and protects the interface
    Forms a thin, controlled, crystalline oxide that stabilizes the surface and preserves a low‑defect interface until the next critical process step. Strong passivation is widely known to suppress interface traps and defect‑assisted recombination, directly improving device consistency and performance.

With ALP™, we significantly reduce interface level defect density, lower leakage, and enable clear yield uplift at advanced nodes.
This is the foundation that modern nanosheet GAA devices require, and precisely what has been missing from the industry’s toolkit.

How ALP™ differs from today’s “clean”

Conventional methods:

  1. Wet cleaning removes chemical contamination. However, it cannot repair atomic‑scale disorder or deep interface traps. Wet processes can introduce carbon contamination into the surface and sub‑surface of silicon, degrading electrical integrity. Additionally, HF/RCA sequences can increase surface roughness and leave dangling bonds, compromising epitaxy and interface quality.   
  2. Plasma cleaning removes residues. However, the risk of silicon damage and new defect formation at advanced geometries. Plasma etch and dry clean steps leave residual Cl/Br species, promote native oxide re‑growth, and can damage sub‑silicon layers, directly degrading device electrical characteristics.

ALP™ is purpose‑built to reset the surface to a low‑defect baseline before deposition/etch steps, so downstream modules (ALD, litho, etch, epitaxy) can realize their full benefit on a clean, ordered interface.  

The outcomes that matter

  • Lower leakage → lower power
    Reducing interface traps and defect‑assisted paths cuts off‑state and junction leakage. This is translating into lower static power and improved device reliability. E.g., with radiation sensors ALP™ reduced the leakage current up to 80% and leakage current variation over 75%, leading to better component performance and reduced calibration costs.
  • Lower variability → higher yield
    Yield is incredibly sensitive to defect density at advanced nodes; even small improvements in defectivity can bend the cost curve materially. Across the industry, a few percentage points of yield at scale can equate to hundreds of millions dollars in value depending on product mix.
  • A path beyond the “atomic wall”
    As nodes shrink and architectures evolve, surface and interface quality become systemically limiting. Tight control at the atomic-level is one of the few remaining levers to extend effective scaling.

“Isn’t this just better cleaning?”  – Not exactly, it’s more than that.

ALP™ is purification + defect suppression + passivation. It bridges a gap between contamination removal and materials engineering. Applying this into logic/AI chips at advanced nodes is overdue – and that’s what ALP™ delivers.

How ALP™ fits into modern fabs

  • Complementary to ALD/ALE and GAA flows. ALP™ improves the starting interface so ALD stacks, spacers, and gate dielectrics can achieve lower Dit and leakage.
  • Aligned with next‑node timelines. Foundry roadmaps anticipate 2 nm mass production in 2025–2026 windows (risk runs started). That’s precisely where atomic‑scale interface control pays off fastest.
  • Economically relevant. With the cost of toolsets and wafers surging at sub‑3 nm, yield elasticity dominates financial outcomes. Improved surface quality is one of the highest ROI levers available.

While new chip architectures and 3D stacking helps us to boost the calculation power, there is a need to turn the new page to enable the Moore’s Law 2.0 – And that is exactly what ALP™ is doing.  It’s the enabler of better yield and new solutions that are needed now and in near future.

FAQ: Atomic Level Purification (ALP™)

Q1: What is ALP™ (Atomic Level Purification)?

ALP™ (Atomic Level Purification) is a semiconductor interface engineering methodology designed to restore atomic lattice order and suppress interface trap density (Dit) at advanced technology nodes.

Unlike conventional wafer cleaning, ALP™ focuses on atomic-level surface purification of silicon before critical deposition or epitaxy steps. It removes embedded contamination, reduces defect-mediated leakage paths, and stabilizes the Si/oxide interface – which has become a first-order limiter at 3 nm and below.

Q2: How is ALP™ different from wet cleaning or plasma cleaning?

Traditional wet cleaning (RCA/HF) removes chemical residues and particles. Plasma cleaning removes surface contamination.

However, these processes:

  • Do not restore near-surface lattice order
  • Cannot fully eliminate deeply embedded atomic contamination
  • May introduce surface roughness or new defect states

ALP™ goes beyond particle removal. It performs atomic level purification and stabilization of the silicon interface, targeting the root causes of interface trap formation rather than only surface residues.

Q3: Does ALP™ reduce interface trap density (Dit)?

Yes. ALP™ is designed to suppress interface trap formation by restoring atomic ordering and stabilizing the silicon surface before high-k or dielectric deposition.

Lower Dit directly contributes to:

  • Reduced subthreshold leakage
  • Lower static power
  • Improved threshold voltage stability
  • Reduced variability in nanosheet GAA devices

As scaling advances, controlling Dit becomes one of the highest-leverage methods for improving yield and reliability.

Q4: Is ALP™ compatible with ALD, ALE, and advanced GAA process flows?

Yes. ALP™ is implemented upstream of deposition and etch modules.

By delivering an atomically purified and passivated interface, ALP™ enables more predictable nucleation in ALD films, improved dielectric integrity, and reduced defect propagation in downstream process steps.

It complements, rather than replaces, existing advanced node toolsets.

Q5: Why does passivation matter for logic/AI chips?
Interface traps near the channel or junction regions increase leakage and variability. Robust passivation suppresses trap‑assisted conduction, improving off‑state power and device consistency.

The ALP™ advantage in one sentence

ALP™ delivers atomically purified and passivated silicon surfaces for next‑node device integrity – reducing leakage, stabilizing variability, and unlocking yield at the point where the industry needs it most.