Atomic-Level Cleanliness: The Next Frontier in Semiconductor Fabrication
In recent years, awareness of surface defects has increased but not yet fully realized in the semiconductor industry. This is due to several factors, ranging from missing suitable characterization tools at fabrication lines to the lack of solutions to tackle these issues.
For decades, semiconductor fabrication has focused on minimizing defects. However, as node size shrinks and technical demand increases, focusing solely on classical defects is no longer sufficient. We need to turn our attention to atomic-level defects as well.
At SisuSemi, we are not alone in recognizing this challenge.
In his article (https://ieeexplore.ieee.org/document/10545526 ), Jeff J. Ye, (a process integration engineer from Micron Technology), highlights the impact of atomic-level cleanliness on yield issues in semiconductor fabrication, particularly in DRAM memories.
Ye points out that plasma etch processes introduce defects that significantly affect yield. He concludes that defects and line roughness are major yield detractors in advanced bitline dry etching processes in high-volume DRAM manufacturing.
Ye identifies several key issues caused by atomic-level defects:
Plasma etching by-products: Carbon-based polymers and silicon-oxide residues are difficult to remove with classical methods, leading to yield loss.
Line width variations: These can degrade performance and cause inconsistencies in device fabrication, especially in DRAM bitlines.
Residue accumulation: This impacts subsequent wafers, leading to inconsistent performance and yield.
Uneven surfaces: Rough semiconductor layers create imperfections that reduce overall device functionality.
The Novel Solution
At SisuSemi, reducing surface defects and contaminants are at the core of our technology. While we do not change the etching process, we ensure that wafers are as contaminant-free as possible. Our technology can clean, reorder the crystal structure, and passivate etched wafers for subsequent steps.
Our solution is based on an elevated temperature ultra-high vacuum process that removes contaminants at low temperatures and reorders the crystal structure. Specifically, SisuSemi’s solution:
Removes by-products from silicon surfaces while reordering the atomic-level crystal structure before adding a stable crystalline silicon dioxide passivation layer.
The contamination-free and restored crystal structure has been verified with XPS*, TEM*, and other surface analysis methods.
Minimizes surface defects, reducing the trapping of etching by-products.
SisuSemi’s solution has demonstrated 42% reduction in the interface defect density compared to the state-of-the-art MOSCaps
· Minimizes linewidth variation by creating crystalline structure providing atomic-scale smoothness on the surface.
The smooth surface on atomic level is verified e.g. by STM*, TEM*, and LEED*.
Additionally, our cleaning treatment can be applied before etching steps, minimizing cross-contamination in the chamber.
From Challenge to Solution
The semiconductor industry is at a pivotal moment where classical defect management is no longer sufficient. At SisuSemi, we recognize these challenges and have developed a novel technology to tackle them head-on.
Our solution has demonstrated significant improvements in surface cleanliness and defect reduction , verified through advanced surface analysis methods. By minimizing surface defects, reducing the trapping of etching by-products, and providing atomic-level smoothness on the surface we can enhance yield, performance, and consistency across wafers.
With the help of our novel technology, we can provide a significant step in atomic-level cleanliness that helps you boost your yield, reduce power consumption, and increase your component lifespan.
*Metrology tools acronyms:
XPS, x-ray photoelectron spectroscopy
TEM, (scanning) transmission electron microscopy
STEM, scanning tunneling microscopy
LEED, low energy electron diffraction
