The Impact of Surface Quality Increases as Node Size Decreases
The surface quality and roughness that was still acceptable with 60nm+ linewidths is catastrophic with node sizes of 10 nm and below. With the smaller node-sizes transistors are mainly constructed from a surface, increasing the importance of its cleanliness at atomic level as well as it’s smoothness.
In semiconductor fabrication people have been focusing on minimizing defects for decades. It should be noted that as node sizes decrease, the traditional methods focussing to particles and other contaminants is not anymore enough alone. We need to start to look ways to improve the cleanliness and surface quality at atomic level as well.
Figure 1* - What was acceptable roughness at 60nm+ linewidths, can be a catastrophic defect at node sizes of 10nm and below.
The same demand has been investigated and reported in different research and studies. As example in their paper, Chen et al. (https://ieeexplore.ieee.org/document/1210828) describe the importance of atomic-level smoothness. Based on Chen at al., with CMOS technology, the quality of the Si-SiO₂ interface becomes critical when scaling below 100nm dimensions.
Here it’s important to remember that classical methods used don’t provide the best results. The fundamental sources of interface quality lie in the atomic-level quality of silicon and silicon dioxide.
Sources of Poor Smoothness and Si-SiO₂ Quality Issues
The sources of poor smoothness and Si-SiO₂ quality can be attributed to two major factors:
1) Silicon Surface Quality: The quality of the silicon surface is the starting point. Without a smooth and clean surface, achieving a smooth interface is impossible. Various contributors to this include contaminants like carbon, hydrogen, and oxygen, which cause atomic-level roughness. Even if these contaminants are cleaned, non-ordered silicon atoms near the surface remain due to different processing steps and earlier bonds with the contaminants.
2) SiO₂ Quality: The native oxide is not crystalline, and most oxidation methods do not provide crystalline surfaces. Hence, even if the surface is smooth initially, the SiO₂ quality does not support a smooth outcome.
Effects of Poor Si-SiO₂ Quality
There are a few key effects coming from the poor Si-SiO₂ interface and quality. Based on Chen et al. the key effects are.
1) Effect of Oxide Thickness on Roughness: Reducing interface roughness results in improved chip characteristics.
2) Improved Drive Currents and Mobility: Devices with reduced interface roughness (1.1 Å rms) showed improved drive currents by 5% in NMOS and 17% in PMOS transistors. A smoother interface enhances transistor mobility and electrical performance.
3) Transistor Performance Enhancement: The transconductance of devices with reduced roughness was enhanced, as seen in NMOS and PMOS transistors, demonstrating improved current-voltage characteristics. This improvement shows that optimizing interface roughness directly leads to higher transistor performance.
The work done with SisuSemi aligns perfectly with these findings and underscores the importance of surface smoothness and atomic-level cleanliness.
With our advanced surface treatment technology, we can significantly reduce interface roughness, leading to enhanced chip characteristics. Our solutions have demonstrated a 42% reduction in interface defect density, improving charge carrier mobility and reducing energy losses. Additionally, we achieved a 67% reduction in leakage current, enhancing power efficiency and device reliability. By optimizing the oxide interface, we directly enhance transistor performance, resulting in better current-voltage characteristics and overall device stability.
Solution
There are multiple solutions to address this issue. However, classical solutions do not tackle all roughness sources listed above.
Now, there is a new solution available that addresses all these factors providing the state-of-the art surface quality for semiconductor fabrication.
SisuSemi’s solution utilizes vacuum technology and elevated temperatures to:
1. Remove contaminants from the surface,
2. Re-order atoms near the surface, and
3. Provide a smooth crystalline SiO₂ protection layer.
Conclusion
As we move to smaller node sizes, the relative size of the surface increases and becomes a major factor. Without atomic-level cleanliness and a smooth protection layer, many active defect stages remain, causing issues with component performance and reliability. Classical solutions don’t tackle all the sources of poor interface quality, but the novel solution from SisuSemi does.
*)Image created with ChatGPT for illustrative purpose
