Connecting surface quality to device performance in semiconductor manufacturing

A semiconductor surface can meet its roughness specification while the finished device still shows excessive leakage or unstable electrical characteristics. This is important when it threatens a device specification, reduces electrical yield or delays qualification.

If established process adjustments have not resolved the problem, a surface or interface contribution may be worth investigating. The starting point is an observed device limitation and a testable hypothesis about its cause. Atomic-level defects are one possible explanation – their importance must be established for the product and process concerned.

A review published in Nanomanufacturing and Metrology in September 2026 examines plasma-based atom-selective etching (PASE), an atmospheric plasma process for selectively removing surface atoms. The authors describe progress in atomic-scale polishing, alongside challenges in uniformity, thermal stress and oxidation.

The authors note that devices based on PASE-polished surfaces had not yet been reported in the literature they reviewed. They also flag potential electronic defects from plasma-generated ultraviolet radiation. This reinforces the need to connect surface measurements to device results.

Four complementary views of semiconductor surface quality. Conceptual illustration, not to scale and not experimental data.

The illustration separates four complementary questions. Surface topography describes roughness, steps and pits. Surface chemistry concerns residues, adsorbates and the intended termination. Atomic structure concerns ordering and defects near the surface or interface. Electrical measurements show how the resulting structure or device responds under the tested conditions.

For an IDM, foundry or OSAT, the useful connection is between a change in those surface properties and the device parameter that limits the product. Evidence of a smoother surface or a more ordered interface needs to be linked to electrical performance before drawing conclusions about yield or reliability.

At SisuSemi, this connection guides how we propose evaluating Atomic-Level Purification (ALP). Our process uses ultra-high vacuum, temperatures below 450 °C and controlled oxidation. It is designed to clean silicon surfaces, improve atomic ordering and form a thin protective silicon dioxide layer. Suitability depends on the material stack, temperature exposure and requirements of the following process steps.

Our company-reported metal–oxide–semiconductor capacitor (MOSCap) case summary describes an evaluation involving a silicon/aluminium oxide interface. ALP-treated structures showed a 42% reduction in interface defect density and a 67% reduction in leakage current compared with a chemically grown oxide reference. The summary also reports structural characterization by scanning transmission electron microscopy. These results concern the tested structures and conditions – another device or manufacturing route needs its own comparison.

The case summary does not provide absolute electrical values, detailed measurement conditions, sample counts or distributions. Those details need to be reviewed before judging transferability. A technical comparison should also establish the dielectric stack, thickness, thermal history and other differences between treated and reference samples. This helps assess whether the results support the proposed mechanism and whether the comparison represents the customer’s process.

A useful feasibility study starts with the affected product requirement and the minimum improvement that would matter. The team should define the electrical metric, reference process and stopping criteria, including unacceptable changes in other critical parameters. Matched reference and treated samples should receive equivalent subsequent processing and measurement conditions. Where practical, the comparison should include the customer’s best feasible alternative treatment.

Surface analysis then helps interpret the result. If the electrical response changes, which chemical or structural changes could explain it? If it does not, what does that reveal about the original hypothesis? Results should be assessed against measurement uncertainty and sample variability. Further development should test whether the benefit is reproducible, improves the relevant device distribution and survives subsequent fabrication, packaging and appropriate stress testing.

Before requesting samples, the teams should identify a candidate insertion point and screen the material stack, full temperature exposure, oxidation requirements and handling route. An off-line evaluation may be suitable if representative downstream testing can be arranged. The process and device owners should agree how treated material would proceed through that route and what would make the evaluation stop. Repeatability, total cycle time and cost per good device then inform the case for further development.

A technical gain should have a credible route to business value, such as more devices meeting specification, less scrap or a qualification issue resolved. That value must justify evaluation, integration and operating costs. Continuing with the current process or making a simpler adjustment remains a valid outcome when it meets the product’s needs.

If an unresolved electrical issue is affecting your product performance or manufacturing results, contact SisuSemi for an initial applicability discussion. You can start with an anonymized description of the symptom, the metric that matters and broad process constraints. Together, we can assess whether a surface or interface contribution is plausible and whether an ALP comparison is worth designing. A feasibility study would follow if the problem, compatibility and value of the proposed test justify it.

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The physics have turned against “good enough” cleaning

As the industry moves to gate-all-around (GAA) nanosheet transistors at the 2nm node, the interface between the channel and the gate dielectric — and between nanosheets themselves — becomes the dominant source of device variability. Industry analysis of GAA metrology at 2nm makes the point directly: interface defects and contaminants at these buried, nanometer-scale surfaces turn into leakage paths and performance killers, and detecting them without destroying the device is now one of the hardest problems in the fab. Legacy particle-counting clean processes were built for a world where clean meant free of visible debris. They were never designed to police single atomic layers. SisuSemi has made the same argument in its own technical writing, framing atomic-scale surface purity as the binding constraint behind AI chip performance and yield. The point is novel because the industry’s own device physics has arrived at the same conclusion at the same moment SisuSemi has a commercial product to address it.

The market has already priced purity as a billion-dollar category

Investors don’t need to take this thesis on faith; the M&A market has already underwritten it. In 2021, Entegris paid 6.5 B$ for CMC Materials specifically to consolidate its position in the high-purity chemicals and CMP slurries used to clean wafers between fabrication steps, a deal analysts flagged as making Entegris a top-five global player in semiconductor materials. Two years later, Fujifilm paid 700 M$ for the high-purity process chemicals business Entegris had to divest, explicitly to strengthen its position in the growing segment of wafer etch-and-clean chemistry. Those transactions confirm what the category is worth to strategic buyers today, before the GAA transition has even fully ramped. A differentiated, atomic-level technology entering the category now enters a market that has already demonstrated it will pay a premium multiple for purity leadership.

Fabs are building now — and buying now

The scale of current capital deployment is the part investors underestimate. TSMC has raised its 2026 capex guidance to 60–64 B$, up from an already-record 52–56 B$, on the back of AI-driven demand it says shows no sign of slowing. ASML’s EUV lithography systems now carry order lead times stretching to 2028, and SEMI projects global semiconductor equipment revenue will grow 70% over three years as fabs race to add capacity. IDC now forecasts the global semiconductor market will cross 1.29 T$ in 2026, up more than 50% year over year. This matters for SisuSemi’s timing specifically: process and tooling decisions for next-generation fab lines are being locked in now, not in ten years. A yield- and performance-enhancing process step that isn’t qualified into these build cycles misses them for a decade. The window to get ALP designed into new and upgraded lines is open precisely because so much new capacity is being specified during next years.

Europe Is funding this exact bet

For a European deep-tech company, the policy backdrop matters as much as the technology. The European Chips Act has already mobilized more than 80 B€ in chip-related investment against an original 43 B€ target, and the European Commission’s proposed Chips Act 2.0 is targeting 120 B€ by 2035, with explicit emphasis on advanced-node capability. Meanwhile, imec.xpand — one of Europe’s most active deep-tech semiconductor investors  — has deployed its 300 M€ fund across 32 portfolio companies that have collectively raised nearly 1.5 B€, including two unicorns. Capital earmarked for exactly this category, at exactly this stage, is larger and more active in Europe today than at any prior point in SisuSemi’s history.

The precedent: European deeptech can own a global category

Skeptics of Finnish dee tech should look at Bluefors. Spun out of Aalto University’s low-temperature laboratory in 2008 into ultra-low-temperature cryogenics for quantum computing, Bluefors is now cited by Finland’s national investment agency as one of the country’s clearest examples of a university-rooted deep-tech company becoming a global market leader, alongside ICEYE and Oura. SisuSemi shares the same origin pattern — University of Turku materials research, patents dating to 2015, a hard-tech problem with no easy substitute — entering its commercial window as its category’s underlying demand is accelerating rather than plateauing.

The investment case

None of these four forces alone would make the case. Together, they describe an opportunity window: a physical inflection point that makes atomic-level purity newly essential, a strategic M&A market that has already validated the category’s value, a fab investment supercycle deciding its tooling roadmap right now, and a European capital and policy environment built to fund exactly this kind of company. For investors evaluating SisuSemi as an investment target, the question isn’t whether atomic-level purification becomes standard in advanced semiconductor manufacturing — the physics and the M&A record both suggest it will. The question is whether early investors participate while the category is still being defined, or after it isn’t.

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“Semiconductor manufacturers are too conservative to work with an unproven startup” treats conservatism as a wall — a fixed, structural refusal that no amount of good technology gets around quickly. That’s not quite right, and the industry’s own qualification literature makes the actual picture clearer: semiconductor manufacturing has one of the most detailed, well-documented playbooks of any industry specifically built to let a risk-averse organization work safely with new, unproven materials and suppliers. Conservatism here isn’t a blanket no. It’s a procedure. And procedures can be navigated.

Qualification doesn’t start with a full commitment — it starts with a fraction

The semiconductor industry’s published literature on process-change qualification describes a staged approach. A 2019 open-access study presenting a qualification framework used in a wafer foundry describes a Pre-Change Qualification stage, where preliminary data are gathered before production exposure, followed by Change Qualification on actual production wafers to compare the changed process with standard conditions and evaluate output and reliability-related data. Confirmation pilot lots and engineering lots are then used to verify flow stability and yield before processes and tool sets are fixed within agreed control limits. The scale and duration depend on the risk and criticality of the change, but the logic is consistent: constrain exposure first, then expand only when the data support the change.

Read that carefully: the entry point into a fab’s production environment for a new process or material is not “convince us it is safe and we will switch everything over.” It is closer to “run a bounded, customer-approved qualification on controlled production or engineering lots, compare it with the existing baseline, and let the data make the case.” That is a fundamentally different bar than the one implied by “customers are too conservative to try something new” – it is a bar a startup can address with a well-designed qualification program and honest data, not one that requires eliminating all risk before the conversation even starts.

Named standards, not ad hoc gatekeeping

This is not an informal or arbitrary process either. Semiconductor companies operate within multiple named, formal qualification frameworks. JEDEC’s current JESD47L defines a baseline set of stress-test-driven acceptance tests for qualifying new integrated-circuit products, product families and products affected by process changes. MIL-STD-883 establishes uniform test methods and controls for microelectronic devices intended for military and aerospace applications. The Automotive Electronics Council’s AEC-Q100 defines failure-mechanism-based minimum stress-test qualification requirements for automotive integrated circuits. These standards do not replace each fab’s internal supplier and process qualification rules, but they illustrate the same broader principle: risk is managed through defined evidence, test conditions, acceptance criteria and controlled release – not a single all-or-nothing judgment call made on trust.

Wafer-level reliability practice follows the same logic beyond the initial qualification gate. Texas Instruments’ published reliability guidance notes that new processes and device technologies receive extensive qualification, while variations of existing processes may receive less extensive qualification. After initial qualification, wafer-level reliability monitors are used to confirm that fab processes remain in control and continue producing die to the fabrication baseline. Qualification, in other words, is not a single leap from “unproven” to “in production”; it is part of a continuum from evidence before release to monitoring after release.

The industry is actively working to make this pathway faster, not slower

If qualification friction were simply the unavoidable price of doing business in a conservative industry, there would be little incentive to reduce it. Instead, companies are developing dedicated qualification aids to streamline parts of this bottleneck. One concrete example is Chipmetrics’ PillarHall family of standardized test chips, which is marketed for faster and more repeatable qualification of semiconductor deposition tools and processes, reducing the time, material consumption and analytical burden associated with conventional qualification approaches. That does not make qualification easy, but it shows that qualification overhead is treated as an engineering and productivity problem that can itself be improved.

What conservative actually means for a startup navigating this

None of this means qualification is fast or easy. Production-representative data, reliability evidence, internal change approvals and repeatability all create a genuine bar to clear, and the exact duration depends heavily on the risk and process criticality involved. But it is a specific bar with a known structure, not an undefined wall of institutional distrust. “Customers are too conservative to work with startups” often turns out, on closer inspection, to mean “the vendor has not yet entered – or has not yet successfully navigated – the qualification pathway that exists for process changes.” That is a process problem that can be managed, not evidence that the door is closed.

That reframes the actual task. The job is not inventing trust from nothing in a room full of skeptical engineers. It is entering the existing playbook correctly – starting with a bounded feasibility or qualification exercise, agreeing measurable KPIs, generating comparative data against the customer’s baseline, and expanding the engagement only when the evidence warrants it. SisuSemi’s current feasibility offering is structured around exactly this entry point: agree scope and KPIs, perform pre-measurements, treat customer wafers or components, perform post-measurements, analyze the improvement potential and return the samples so the customer can continue its own process flow. That is not asking a fab to make an exception; it is aligning the commercial entry point with the staged, evidence-based qualification logic the industry already uses.

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The category-level numbers 

According to Tracxn’s 2026 sector data, the semiconductor manufacturing equipment sector has recorded 116 acquisitions and 172 IPOs across its tracked company universe — a combined exit rate of roughly 12.1%, more than double the 4.7% exit rate Tracxn reports for technology companies generally. That’s a striking gap for a category often assumed to be a difficult, capital-intensive niche. SME’s narrowness is precisely what makes it exit-friendly: a small number of dominant strategic acquirers with both the balance sheet and the structural incentive to buy specialized capability rather than build it internally, combined with public markets that have repeatedly shown appetite for pure-play companies once they own a defensible, well-understood niche. 

A global proof point: Kokusai Electric 

Kokusai Electric, a Japanese deposition and thin-film equipment maker, offers one of the clearest recent illustrations of this dynamic outside Europe. KKR acquired the business from Hitachi Kokusai Electric for 2.2 B$ in 2017-2018 — a private-equity buyout of a specialized, narrowly-focused semiconductor tool maker most investors outside the industry had never heard of. Five years later, in October 2023, Kokusai listed on the Tokyo Stock Exchange in Japan’s largest IPO in five years, raising roughly 724 M$. Shares jumped as much as 32% on debut, valuing the company at approximately 3.6 B$ — nearly 65% above KKR’s original purchase price. A specialized equipment maker serving a niche most generalist investors couldn’t name went from private-equity buyout to a multi-billion-dollar public listing inside five years, purely on the strength of owning a defensible process niche. 

Europe’s own version of this story 

Europe’s clearest example follows a similar storyline, and it’s now a decade into proving it wasn’t a one-off. VAT Group, a Swiss maker of high-end vacuum valves for semiconductor manufacturing, was taken public on the SIX Swiss Exchange in 2016 by its private-equity owners, Partners Group and Capvis, in an offering valued at up to roughly 635 M CHF. VAT wasn’t a broad, diversified industrial conglomerate — it was, and remains, a narrowly-focused specialist in one specific, mission-critical category of semiconductor process equipment. Nearly a decade later, VAT reported 942 M CHF in net sales and 212 M CHF in net profit for 2024, commands roughly 75% global market share in semiconductor vacuum valves and trades as a substantial, dividend-generating public company. That’s the trajectory a genuinely narrow, technically deep European SME specialist can follow, sustained over ten years of public-market scrutiny rather than a single favorable listing day. 

Europe has also produced a clean acquisition-path example in the same category. SPTS Technologies, a wafer-processing equipment maker headquartered in Newport, Wales, was acquired by Israel’s Orbotech in 2014 for 215 M£ — a UK-founded specialist bought outright by a larger strategic player in an adjacent part of the electronics manufacturing ecosystem. The story didn’t end there: Orbotech, with SPTS now inside it, was itself later acquired by KLA, one of the small handful of dominant global semiconductor equipment strategics. A specialist company that started in Wales ended up folded into one of the industry’s largest players through two successive rounds of strategic consolidation — exactly the kind of multi-stage exit pathway a narrowly-focused European SME company can realistically follow. 

Why strategics keep buying rather than building 

The buyer pool behind these deals isn’t very broad, but it is active and well-capitalized. Major SME (Semiconductor Manufacturing Equipment) vendors, such as Applied Materials, Lam Research, KLA, Tokyo Electron and ASML, dominate the strategic acquirer landscape for specialized process technology, and their own economics make acquisition an attractive alternative to internal development: major equipment platform R&D in this industry runs three to five years and regularly exceeds 500 M$ per platform. In addition, major IDMs (Integrated Device Manufacturer) and foundries, such as TSML, Samsung and Intel, have a strong incentive to differentiate their business by securing access to novel technologies. Against that backdrop, acquiring a startup that has already proven out a narrow, differentiated capability is frequently the more capital-efficient path for a strategic than competing it internally from scratch — which is a structural reason this category keeps producing real M&A activity rather than relying on IPOs alone. 

Where this leaves a company like SisuSemi 

None of this guarantees any specific outcome — exit data describes a category’s tendencies, not any individual company’s future. But the pattern is consistent and well-documented across both routes: a narrow, defensible, technically deep SME specialist has a real, evidenced path to either a strategic acquisition by one of the industry’s small set of dominant buyers, or, with enough scale, a public listing that markets have shown genuine appetite for. SisuSemi sits in exactly the category — narrowly focused, technically deep, serving an industry whose acquirers and public markets have both demonstrated, repeatedly and recently, that they know how to value a specialist like this once it proves itself out. 

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Transformative semiconductor technologies rarely move directly from the laboratory into high-volume manufacturing. They begin as difficult research questions, progress through years of experimentation and equipment development, and become commercially essential when the industry encounters problems that established processes can no longer solve. Atomic Layer Deposition, or ALD, followed this path. Its evolution from a specialized thin-film technique into an enabling technology for modern semiconductor manufacturing provides a useful—although not exact—parallel for SisuSemi’s Atomic-Level Purification, or ALP, technology.

The comparison is particularly compelling because both technologies have strong roots in Finnish research.

The Finnish ALD story began in the 1970s, when Dr. Tuomo Suntola and his colleagues developed Atomic Layer Epitaxy, initially for manufacturing high-quality zinc sulphide films for electroluminescent displays. The first patent application was filed in 1974. Historical research has also established that related concepts had been studied earlier in the Soviet Union under the name “molecular layering.” ALD therefore has more than one scientific origin, but Suntola’s Finnish work was decisive in developing production-capable reactors, industrial applications and the commercialization path associated with modern ALD.

ALD did not become indispensable overnight. Its first applications were narrow, the available material combinations were limited, and production equipment had to become faster and more reliable. The technology nevertheless offered a distinctive capability: thin films could be grown through repeated, self-limiting surface reactions, providing exceptional control over thickness and conformality. As researchers expanded the range of materials and applications, ALD moved from displays into photovoltaics, catalysis and semiconductor devices.

Its commercial relevance increased as semiconductor structures became smaller, more three-dimensional and less tolerant of variation. In the early 2000s, semiconductor adoption accelerated and both research and business activity expanded rapidly. A visible industry milestone came in 2007, when Intel introduced 45-nanometre processors using hafnium-based high-k gate dielectrics and metal gates. Intel described the change as its biggest transistor-material advance in around 40 years. The new gate stack reduced gate leakage by more than tenfold compared with the silicon-dioxide approach it replaced. In 2025, global ALD systems market size was 3.18 B$, and it is projected to grow to 10.71 B$ by 2035.

The lesson is not simply that one Finnish technology became globally successful. ALD shows how the value of a deep-tech process platform can increase as semiconductor manufacturing approaches physical limits. Its ability to produce controlled, conformal films became increasingly important because device architectures evolved in a direction that required precisely those characteristics.

SisuSemi’s ALP technology is at a much earlier commercial stage, but it addresses another increasingly important challenge: the atomic condition of semiconductor surfaces and interfaces before and between critical process steps.

ALP originates from materials research at the University of Turku. SisuSemi states that its first underlying patents date from 2015 and that university-developed intellectual property has been transferred to the company for commercialization. University researchers have reported work on ultra-high-vacuum and chemical treatments intended to reduce semiconductor surface defects, electrical leakage and optical losses. A 2025 doctoral study connected with this research demonstrated that UHV pre- or post-treatment could reduce defect density and leakage current in silicon devices.

SisuSemi’s ALP process combines ultra-high vacuum, controlled oxidation and temperatures below 450 °C. According to the company, it removes atomic-scale contaminants, restores order at the silicon surface and forms a very thin crystalline silicon-dioxide layer that protects the treated surface and supports subsequent processing. This matters because conventional cleaning can remove particles and residues while still leaving hydrogen, carbon, disordered oxide structures or electrically active defects at critical interfaces.

The parallel with ALD is not that the technologies perform the same function. ALD deposits controlled material layers. ALP prepares, purifies and restructures the surface on which semiconductor structures are formed. Utilized in tandem, ALP will enhance the results achieved with the ALD. The parallel lies in their development logic. Both rely on atomic-scale control. Both require specialized equipment, repeatable recipes, extensive characterization and evidence of device-level value. Both must ultimately prove compatibility with demanding fab environments.

SisuSemi has also begun moving from research equipment toward industrial compatibility. In March 2026, the company announced an ALP platform supporting wafers up to 300 millimetres, using laser-based heating in an ultra-high-vacuum system. Its stated roadmap includes integration into existing production lines and development toward high-volume manufacturing tools. These are the kinds of equipment and scalability steps that were essential to ALD’s transition from scientific principle to industrial process.

For strategic semiconductor partners, ALP creates an opportunity to identify where atomic-level purification produces the greatest measurable value. Collaboration could examine treatment before deposition, bonding, passivation or other interface-sensitive operations. Joint work with IDMs, foundries, equipment manufacturers and research institutions can validate benefits while addressing throughput, automation, contamination control, process monitoring and factory integration.

For venture investors, the ALD precedent highlights both the patience required by semiconductor deep tech and its potential defensibility. A new process platform needs capital for equipment engineering, application development, intellectual property, customer trials and qualification. Once integrated into a qualified manufacturing flow, however, it can become difficult to replace. Long qualification cycles, process know-how and customer-specific recipes can create durable competitive advantages and long commercial relationships.

ALD’s success does not guarantee that ALP will follow the same path. ALP must still demonstrate repeatable customer results, attractive economics, scalable throughput and compatibility with established semiconductor processes. Nevertheless, the strategic pattern is familiar. Semiconductor scaling is creating a growing need to control not only deposited layers, but also the atomic quality of the surfaces beneath them.

ALD gave manufacturers the ability to build critical films with atomic-scale precision. ALP aims to ensure that those films and devices begin from a cleaner, more ordered and more reliable atomic foundation. Finland’s ALD experience shows that a specialized research breakthrough can become globally important when its unique capability aligns with an emerging industrial necessity. For investors and semiconductor partners, the opportunity is to see whether ALP can become the next Finnish atomic-level technology to make that transition.

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AI chipmakers are challenging one of semiconductor manufacturing’s most basic assumptions: cut the wafer into many smaller dies, package them separately, and connect them at the system level. A more ambitious path is to push far larger compute fabrics onto a single silicon substrate, using wafer-scale or near-wafer-scale designs to reduce communication bottlenecks and keep more AI compute close to memory. The result is a new class of extremely large accelerators whose value depends not only on architecture, but on whether the underlying wafer can be made cleanly and consistently enough to function as one integrated computing surface.

But there is a physics problem baked into that ambition, and it only gets harder as large AI accelerators move toward denser interconnects, higher transistor counts and more advanced process nodes. It is a problem that SisuSemi is built specifically to address with its Atomic-Level Purification (ALP) technology.

Bigger wafers, bigger bets on cleanliness

Every semiconductor fab fights the same enemy: contamination. Trace metallic ions, particulates and residual chemistry left behind during etch, deposition and back-end-of-line (BEOL) interconnect formation can turn a working transistor into a dead one. For a conventional accelerator die — maybe 800 square millimeters, cut from a wafer alongside dozens of siblings — a contamination event ruins one die. Fabs simply bin the bad ones and ship the good ones.

Large-area AI accelerators do not get that luxury. When more of the wafer becomes part of a single functional compute fabric, a contamination hotspot is no longer just a bad die among many — it can become a local wound in the system itself. Designers can engineer around some defects with redundancy, spare cores, rerouting and fault-tolerant architectures. But those strategies are, fundamentally, a tax. Every resource sacrificed to a contamination-induced defect is a resource that is not doing AI compute, and every redundancy budget has limits.

This is where atomic-level purification stops being a nice-to-have and starts looking like a structural necessity for wafer-scale economics.

What atomic-level purification actually changes

SisuSemi’s ALP platform, delivered through its AtomSeal product line, targets contamination control at the atomic scale — the regime where a handful of stray ions per square centimeter can determine whether an advanced-node transistor or interconnect behaves as designed. This matters most in exactly the process steps AI chip maker depends on most heavily: BEOL interconnect formation, where the metal layers that stitch hundreds of thousands of cores together are built up layer by layer, and where atomic-scale residues can quietly degrade conductivity, increase leakage or create latent reliability failures that don’t show up until a chip is under sustained load.

For a company selling small dies, a BEOL defect might cost a customer a single unit. For wafer-scale or very-large-die AI accelerators, a systemic BEOL contamination issue can compromise the interconnect fabric that allows many compute regions to behave like one coordinated processor. The larger the compute surface, the more opportunities there are for a defect to hide inside the wiring that matters most.

Four ways ALP could strengthen wafer-scale AI economics

1. Yield economics at unprecedented die sizes. Large-area yield math is brutal: defect probability compounds with area. Atomic-level purification attacks the defect density itself, rather than asking redundancy to keep absorbing the hit. Even a modest improvement in contamination-driven defect rates translates into meaningfully more usable silicon per wafer — and at the price points of advanced AI accelerators, that shows up directly in gross margin.

2. Protecting the redundancy budget. Fault-tolerant architecture is a strength, but it is also a finite resource designed against an assumed defect rate. Lower the atomic-level contamination baseline, and the same redundancy budget goes further — either as higher effective compute availability per wafer or as headroom to push performance and power delivery harder without eating into reliability margins.

3. Interconnect integrity for cross-reticle stitching. As WSE generations add cores and push memory bandwidth higher, the demands on interconnect purity rise in lockstep. Atomic-level contamination control in BEOL processing directly supports the signal integrity that cross-reticle stitching depends on — a more fragile requirement at wafer scale than at die scale, simply because there’s so much more interconnect for a defect to hide in.

4. Runway toward more advanced nodes. As AI accelerators move toward denser interconnects, higher transistor counts and more advanced process technologies, atomic-scale contamination tolerances tighten dramatically. Purification technology built for that regime becomes less of an efficiency play and more of a gating requirement for future roadmaps.

The strategic fit

Advanced AI accelerators compete in a capital-intensive race where performance, power efficiency, yield and reliability all matter. In that market, differentiation increasingly comes from manufacturing execution, not just architecture. A partner focused specifically on atomic-level contamination control — rather than a general-purpose materials supplier — offers something narrow but valuable: a way to defend the yield and reliability math that very-large-die and wafer-scale computing uniquely depend on, at exactly the process steps where there is the least room for error.

Wafer-scale computing was, for years, dismissed as impractical because making silicon that clean, that consistently, at that size seemed out of reach. As the AI infrastructure market pushes toward larger and more integrated accelerators, the next competitive battle may be won or lost at the atomic level — in the purity of the process that puts those architectures on silicon in the first place.

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Venture investors have spent the last decade rewarding software for its margins and speed of scale, and hardware has often been treated as the slower, capital-hungrier cousin. In semiconductor deep tech, that reputation deserves a second look. The same physical characteristics that make hardware harder to build are exactly what make it harder to displace once it’s installed — and that combination of switching costs, defensibility, and recurring revenue is where some of the most durable returns in this industry actually come from. 

Switching costs are built into the floor of the fab 

Once a piece of process equipment is qualified into a production line, ripping it out is expensive, slow and risky — every fab requalification cycle threatens yield stability that took months to achieve. This is the same dynamic behind the world’s largest equipment franchises. ASML’s non-system business — service contracts and field upgrades on machines already sitting in customer fabs — grew 26% to roughly €8.2 billion in 2025, now approaching a quarter of the company’s total revenue, driven almost entirely by the expanding base of systems it has already sold. That revenue exists only because customers can’t easily walk away from tools already embedded in their process flow. 

For a company like SisuSemi, whose ALP technology is applicable at multiple stages of the manufacturing process — not just post-etch, but potentially across several process steps within the same customer fab — each additional installed system compounds this effect. A single qualified tool becomes the foothold for the next one, inside the same account. 

A moat competitors can’t simply fork 

Software differentiation is often a feature release away from being copied. Hardware differentiation is not. SisuSemi’s ALP process is built on a patented approach combining controlled oxidation, ultra-high vacuum processing and precision heating — the kind of physical, materials-science IP that a competitor cannot replicate by hiring a few engineers and shipping a patch. That’s a different competitive position than most software categories offer, and it’s a large part of why strategic acquirers pay premiums for hardware and materials businesses in this space: Entegris’s 6.5 B$ acquisition of CMC Materials — a company supplying the chemical-mechanical planarization materials used between fabrication steps — was explicitly justified as a way to expand “content per wafer” that couldn’t easily be sourced elsewhere. 

The real prize: revenue that grows with the installed base 

The most attractive part of the hardware model isn’t the initial system sale — it’s everything that follows. Applied Materials’ services division generated a record $6.4 billion in fiscal 2025, with more than two-thirds of that revenue now coming from subscriptions rather than one-off spare-parts orders, growing faster than the underlying equipment business itself. That’s the annuity that makes hardware businesses compound: every system sold becomes a long-lived source of maintenance, spares, calibration and paid upgrade revenue for the life of the tool, often a decade or more. For SisuSemi, this points toward a natural second revenue layer beyond the initial ALP system sale — ongoing consumables, process recipe updates and performance upgrades as node requirements tighten. 

AI and remote monitoring turn hardware into a platform 

The next stage of this model is already visible in how incumbents are evolving their service businesses: Applied Materials describes itself as “rapidly adopting AI and digital tools” across its installed base to shift service delivery from reactive repairs toward predictive, remotely diagnosed maintenance. Once a hardware platform is instrumented and network-connected, it stops behaving like a static capital good and starts behaving like a data platform — every additional unit deployed generates operating data that can improve process recipes, predict maintenance needs and justify premium service tiers across the whole fleet. That’s a lever pure-software competitors don’t have access to, because they have no physical footprint generating proprietary process data in the first place. It’s also a natural extension path for SisuSemi as its installed base grows beyond initial pilot deployments. 

Investors are already backing this thesis in semiconductors 

This isn’t a theoretical argument. Hardware-centric deep tech in the chip sector continues to attract large, committed capital: Cerebras Systems, which builds physical wafer-scale AI computing hardware, raised 1.1 B$ on the strength of a hardware architecture competitors can’t simply clone in software. More broadly, semiconductor-sector funding rounds of 100 M$ or more have been rising steadily quarter over quarter through 2025, and the average semiconductor venture deal size sits around 107 M$ — a reflection of how capital-intensive and how differentiated, this category is understood to be relative to software. ACM Research’s rise to roughly 782 M$ in annual revenue in the wafer-cleaning category, built almost entirely on hardware differentiation against much larger incumbents, is a further reminder that new entrants with genuinely better physical performance do get funded, qualified, and scaled in this market. 

The takeaway for investors 

Hardware deep tech asks more of investors up front — longer qualification cycles, more capital to build and demonstrate systems. What it offers in return is a business that’s structurally harder to copy, stickier once installed, and capable of layering recurring service, upgrade and eventually AI-driven monitoring revenue on top of every system sold. For SisuSemi, whose ALP platform can be qualified across multiple steps within the same customer fab, that installed-base flywheel is the core of the long-term investment case — not a side benefit to the initial equipment sale, but the reason the initial sale matters. 

The post Why Hardware Makes Deep Tech a Better Bet: The Investment Case for SisuSemi’s ALP Platform  appeared first on SisuSemi.

Atomic Layer Deposition has earned its place as the workhorse of advanced-node manufacturing. Its self-limiting, layer-by-layer chemistry gives fabs something no other deposition method can match: Ångström-level thickness control and near-perfect conformality across the most complex 3D structures — nanosheet channels, high-aspect-ratio contacts and DRAM capacitor stacks. But ALD’s precision rests on an assumption that is rarely examined closely enough: that the surface it lands on is clean, chemically uniform and structurally ordered. Increasingly, that assumption doesn’t hold — and the gap between what ALD is capable of and what it actually delivers is being decided before the ALD chamber door even closes.

The overlooked variable: What’s already on the surface

ALD chemistry depends on a predictable population of reactive surface sites — hydroxyl groups, dangling bonds in known locations, a lattice that behaves the way the recipe expects. In practice, wafers rarely arrive at the ALD step in that ideal state. Prior wet cleans, plasma etch and implant steps leave behind residual carbon and hydrogen-related fragments, native oxide regrowth, surface roughness and disordered near-surface lattice structure. Research on wet-processed silicon has shown that HF/RCA-type sequences can leave dangling bonds and elevated surface roughness that compromise subsequent epitaxy and interface quality, while plasma-based cleans, though effective at removing residues, can leave halogen species behind and introduce new sub-surface damage of their own. Neither step fully resolves the atomic-scale disorder sitting just beneath the visible surface.

That residual contamination is not be omitted once ALD begins. Independent nucleation studies have repeatedly shown that surface termination and residual chemistry govern how — and how well — an ALD film nucleates: contaminated or chemically mismatched starting surfaces produce nucleation delay and island-style growth instead of uniform layer-by-layer growth, sometimes requiring tens to hundreds of extra cycles before continuous film coverage is even reached. The result is thickness non-uniformity, pinholes and elevated interface trap density (Dit) at the boundary between the new film and the silicon beneath it. Even in advanced DRAM gate stacks, ALD oxide films have been shown to retain unexpected defects and elevated Dit that trace back to the interface they were grown on, not the deposition chemistry itself.

This matters more with every node shrink. In gate-all-around nanosheet transistors at 2–3 nm, the gate wraps the channel on every side, dramatically increasing the surface-to-volume ratio of the active region, and interface trap states now directly influence leakage and device-to-device variability. Interface quality, once a secondary concern behind geometry, has become a first-order limiter of leakage, variability, and yield. Put simply: ALD can only be as good as the surface it is asked to build on.

From atomic defects to business losses

The consequences of an imperfect starting surface don’t stay confined to a lab notebook — they show up on the balance sheet.

Yield. At advanced nodes, yield is extraordinarily sensitive to defect density, and the industry’s own capital spending confirms it: the market for advanced-node wafer defect inspection systems is forecast to grow from roughly 3.0 B$ in 2026 to nearly 8.9 B$ by 2036, as fabs push from statistical sampling toward comprehensive inline inspection specifically to catch nanoscale defects before they propagate through increasingly expensive process steps.

Wafer economics. Those expensive process steps are not abstract. Leading-edge 3nm-class wafers now run in the neighborhood of 17,000–22,000 $ each, and TSMC’s advanced-node portfolio — 7nm and beyond — accounts for roughly three-quarters of its wafer revenue amid surging AI-driven demand and continued price increases. A defect introduced before deposition that later causes a die, a lot, or a qualification cycle to be scrapped is an expensive loss at those price points, and capacity itself is constrained enough that the opportunity cost of a wasted wafer is compounding.

Power and performance. Interface traps and defect-assisted conduction paths drive up subthreshold leakage and static power. For battery-powered and edge devices, that translates directly into reduced runtime and tighter thermal margins — exactly the specifications customers scrutinize hardest.

Reliability and field risk. Variability introduced at the interface propagates into device-to-device spread, threshold voltage drift, and calibration overhead, which can mean costly post-production calibration or elevated field-failure rates in sensor and precision-analog applications.

In short, atomic-level surface defects that predate the ALD step don’t just cause a materials-science curiosity — they erode yield, inflate power budgets, and slow time-to-market at the exact moment the industry can least afford it.

Fixing the surface before ALD ever starts

This is precisely the gap that novel pre-deposition surface engineering approaches are now targeting — and SisuSemi’s ALP (Atomic Level Purification) is a leading example of that category. ALP is not another cleaning step bolted onto the existing wet-clean-plus-plasma sequence. It is an ultra-high-vacuum, temperature-controlled purification and stabilization process applied upstream of ALD, designed to reset the silicon surface to a genuinely low-defect baseline.

Applied before the ALD step, ALP works on three fronts. It removes embedded atomic-scale contamination — carbon and hydrogen-related species that conventional wet and plasma cleans struggle to eliminate without damaging the surface. It repairs and reorders the near-surface lattice, suppressing the defect-mediated leakage paths that show up later as elevated Dit. And it forms a thin, controlled passivating layer that preserves that clean, ordered state until the wafer reaches the ALD chamber — so nucleation begins on a surface the recipe was actually designed for.

The downstream effect is a more predictable ALD process: more uniform nucleation, fewer pinholes, and dielectric films that behave the way the process specification intends. Outcomes from applying atomic-level purification ahead of deposition include a 3–4x reduction in defect density, leakage current cuts of up to 70%, up to a 20% increase in manufacturing yield, and as much as a 50% improvement in battery life for end devices — figures that translate directly into the yield and power metrics fabs are under the most pressure to improve.

Crucially, this kind of solution is complementary rather than competitive with ALD — it doesn’t replace deposition or etch tooling, it makes them more effective, and it is designed to integrate into existing production lines without major disruption.

The takeaway

As transistor architectures push past the point where geometry alone can save them, the industry’s remaining performance headroom increasingly lives at the atomic scale — in the handful of surface layers ALD builds on top of. Treating pre-ALD surface preparation with the same rigor as the deposition step itself isn’t a nice-to-have refinement anymore. It’s fast becoming a prerequisite for getting the yield, power, and reliability that advanced-node roadmaps demand.

The post When the Foundation Cracks: How Pre-ALD Surface Defects Undermine Atomic Layer Deposition appeared first on SisuSemi.

For decades, semiconductor manufacturing progress was described mainly through lithography, transistor dimensions and wafer-scale yield. The research papers reviewed here show that the industry’s attention is now moving deeper—toward individual interfaces, atomic residues, fixed charges, trapped ions, subsurface contamination and even fractions of a monolayer. 

That shift matters to investors and semiconductor professionals because it is not being driven only by university laboratories. Also, engineers from such semiconductor manufacturers like GlobalFoundries, Intel, Samsung Electronics, Micron, Infineon and Nexperia, as well as semiconductor-equipment specialists DISCO and Plasma-Therm, are heavily involved in the research.  

In other words, atomic-level defects and contamination are no longer merely interesting research topics. They are increasingly treated as manufacturing, yield, reliability and product-performance problems by companies that operate fabs, develop memory and logic technologies, build quantum devices and supply production equipment. 

Why scaling turns small imperfections into large business problems 

As semiconductor dimensions shrink, a contaminant atom or electrically active interface defect occupies a larger relative share of the functional structure. 

A Samsung–KAIST paper states directly that sub-20-nanometre integration requires atomic-scale control because infinitesimal elements can profoundly influence device characteristics. The authors identify residual oxide as a major component of interface defects and describe native-oxide removal before polycrystalline-silicon contact or epitaxial growth as a critical technology for DRAM, flash and logic devices. 

The same principle appears in Intel’s 2024 Nature paper. Intel researchers found that single-electron voltage variation could arise from charge defects such as interface traps or fixed charge in the oxide, together with oxide-thickness variation, line-edge roughness and work-function variation. They concluded that further reductions in fixed charge in the high-k stack could improve device behaviour. 

This is especially revealing. When devices are operated at the level of individual electrons, atomic-scale disorder becomes directly visible as a manufacturability and scaling constraint. Intel’s optimized process ultimately achieved 100% gate yield and 99.8% quantum-dot yield, demonstrating how controlling materials, charge and process variation can translate into wafer-level manufacturing results. 

Production-oriented research connects atoms to economics 

The strongest validation is that these studies connect microscopic surface and interface phenomena to measurable fab outcomes. 

A GlobalFoundries’ 2024 paper investigated wafer-edge yield loss in a 0.13-micrometre BiCMOS process. The study linked the RCA cleaning sequence, HF-last immersion and surface chemistry to particle generation, interface degradation, leakage and shorts. 

By removing the SC2 step and shortening HF-last immersion, GlobalFoundries reported a 50–75% reduction in low-edge-yield fallouts, a 79% increase in wafers achieving at least 90% edge yield and a 20.5% tightening of edge-yield variation. 

The lesson is important: even a mature and widely used cleaning sequence can create subtle surface interactions that translate into major production economics. GlobalFoundries concluded that process development must consider not only particle removal but also surface chemistry before sensitive downstream steps such as thin-gate-oxide formation, polysilicon deposition and epitaxial growth. 

Micron reaches a similar conclusion in high-volume DRAM manufacturing. Micron engineers describe defects and line-width roughness as major yield detractors in advanced bitline etching. Their treatment removed chloride residue, strengthened the chamber’s silicon-oxide coating, improved surface roughness by 30% and produced a 0.15% yield gain. 

In a mature memory fab, even a fraction of a percentage point in yield can have considerable commercial value. The Micron paper also warns that some defects can evade inline inspection and electrical probing, only to appear later as customer returns. 

Samsung’s research shows sustained industrial attention 

Samsung’s work provides perhaps the clearest evidence that this is a sustained industrial research priority rather than an isolated topic. Samsung has done a lot of investigations into ionic impurities, residues, interface traps, oxide defects and structural reliability. 

In a published paper Samsung’s DRAM Yield Enhancement and Memory Diffusion Technology teams explain that chlorine and hydrogen introduced during shallow-trench-isolation processing can act as traps and negatively affect DRAM structures. 

Their revised Trench-Ox process reduced interface-trap density, cut tRDL failures by 86%, increased data-retention time by 16% and dramatically reduced single-bit failures after packaging and module processing. Significantly, the process improved two DRAM characteristics normally considered to involve a trade-off. 

A second Samsung paper shows how residues can remain not only on the wafer surface but inside the silicon substrate. Replacing argon with oxygen during dechucking reduced surface chlorine and bromine anions by 93% and 50%, respectively, and reduced these contaminants by one to two orders of magnitude within the substrate. The treatment also reduced the damaged silicon layer and lowered interface-trap density. 

A third paper reports that fluorocarbon residue can survive etching, react during subsequent HF cleaning and form sub-micron particles that reduce manufacturing yield. Nitrogen treatment reduced surface fluorine by 79%, subsurface fluorine by 44% and completely suppressed the observed particle formation. 

The research also found that equipment humidity affects residue behaviour. This demonstrates that contamination control is not a single-step problem: it is an integration problem spanning chemistry, chamber condition, queue time, post-treatment and environmental control. 

Samsung’s 2024 paper produced with Sungkyunkwan University extends the issue from chemical contamination to nanoscale structural defects. The researchers examined shallow-trench-isolation seams that disturbed gate-oxide growth. Their spacer-STI solution increased seam depth by 40%, reduced the seam-area index to zero, increased gate-oxide thickness by 12% and improved breakdown reliability without changing the intended electrical characteristics of the high-k/metal-gate device. 

Cleaning can itself become a source of contamination 

One of the most commercially relevant messages is that contamination does not arise only from obviously “dirty” manufacturing steps. Cleaning and etching processes themselves can introduce or redistribute impurities. 

Infineon’s paper found carbon concentrations of 4.0% after phosphoric-acid nitride etching, 6.0% after buffered-oxide etching and 1.7% after SC1 cleaning. The authors detected organic compounds in the process chemistry and concluded that impurities could be adsorbed or incorporated into silicon during oxide etching. 

The paper links carbon contamination to hydrophobic surfaces, altered oxide growth, dielectric-thickness variation, spurious doping and reduced electrical functionality. Its figures also show incomplete etching and describe carbon incorporated inside the SiOx layer—not merely deposited on top of it—as a cause of electrical drift. 

The earlier Samsung–KAIST dry-cleaning study adds an atomic-scale mechanism. It found that residual fluorine can initiate local native-oxide regrowth and attract moisture or organic material. Surface analysis showed a strong relationship between residual fluorine and reoxidation beginning at Si–F defect sites. 

The key point is not that wet or dry cleaning is inherently superior. It is that every cleaning method changes the atomic termination and chemical reactivity of the surface—and those changes must be understood and controlled. 

The concern also extends beyond front-end transistor fabrication. DISCO and Plasma-Therm reported that plasma dicing generates fluorinated polymer residues on silicon sidewalls and beneath topographical overhangs such as solder balls and microbumps. Some of these areas cannot be reached by in-chamber post-treatment. 

Atomic and molecular contamination control will therefore also matter in advanced packaging, where narrower streets, smaller features and heterogeneous interfaces create new and increasingly inaccessible surfaces. 

What this validates—and what it does not 

The collective evidence presented above validates the importance and urgency of the problem space. Major semiconductor companies are publishing on interface traps, residual oxides, fixed charge, halogens, carbon, fluorocarbon polymers, damaged silicon and nanoscale structural defects because these phenomena affect yield, leakage, variation, data retention, breakdown reliability and customer returns. 

These papers do not, by themselves, validate SisuSemi’s Atomic-Level Purification technology or prove that one solution can address every defect mechanism. They validate the market need, the scientific rationale and the willingness of industrial R&D organizations to invest resources in atomic-level surface and interface control. SisuSemi is in the process of validating application-specific performance, process-integration compatibility, throughput, repeatability and cost of ownership with multiple industry players. 

For investors, that distinction is positive rather than limiting. The papers show that SisuSemi is not trying to create awareness around an invented problem. It is entering a field where leading manufacturers already measure, model and modify atomic-scale contamination because the economic consequences are visible at wafer, device and product level. The discussion above also shows that there is room for technologies capable of delivering repeatable purification and interface conditioning across several process contexts. 

The semiconductor industry’s next gains will not come only from printing smaller features. They will also come from controlling what remains on, beneath and between those features. The scientific community is paying close attention—and, crucially, much of that scientific community is working inside the world’s leading semiconductor companies. 

The post The Industry Is Looking Deeper: Why Atomic-Level Defects and Contamination Have Become a Strategic Semiconductor Priority  appeared first on SisuSemi.

The typical assumption about semiconductor manufacturers is that they’re conservative almost by temperament: risk-averse, slow to change, unwilling to bet a production line on anything unproven. It’s a reasonable assumption in general, and it’s also demonstrably wrong at the exact moments that matter most. The clearest counter-example in modern chipmaking history isn’t a small one. It’s EUV lithography — arguably the riskiest, most expensive, least proven vendor bet the industry has made in decades and one that the industry’s most conservative players didn’t shy away from. They funded it themselves.

The bet nobody should have made, on paper

Extreme ultraviolet lithography took ASML more than three decades and, by some accounts, over $9 billion in R&D spending to bring anywhere near commercial viability. For most of that development period, the outcome was genuinely uncertain — as late as the 2010s, a meaningful share of semiconductor experts doubted EUV could be successfully commercialized at all. This wasn’t a startup with a clever pitch deck asking for a pilot. It was a fundamentally unproven physical approach, requiring breakthroughs in optics, materials and light-source engineering that hadn’t been demonstrated to work reliably at production scale, from a single supplier the industry would become entirely dependent on if it succeeded.

By any normal read of conservative, semiconductor manufacturers should have waited on the sidelines until someone else proved it out. TSMC didn’t. After encountering an early EUV prototype through imec, TSMC chose to partner directly with ASML on its development — a sharp contrast to competitors like Canon and Nikon, whose lithography divisions stayed closed and made comparatively little effort to collaborate externally on the technology. That early bet mattered enormously to how the next fifteen years played out.

The moment conservatism flipped into a funding race

The starkest evidence that fear of falling behind, not caution, was the dominant force in the room came in 2012, when Intel, Samsung and TSMC — direct competitors, in an industry not known for cooperation — collectively acquired roughly 23% equity in ASML specifically to help fund EUV’s continued development. This wasn’t a hedge against a safe bet. It was three rivals jointly bankrolling a supplier whose core technology hadn’t yet been proven to work, because the alternative — watching a competitor secure exclusive early access if it did work — was judged to be the riskier outcome. Caution about the technology was real. It simply wasn’t as strong as the fear of being the one left behind if a rival got there first.

Once one player proved it, the race compressed fast

By 2019, TSMC was shipping high-volume chips built with EUV, and by its own account has stayed roughly a node ahead of Samsung and Intel ever since. Samsung, meanwhile, brought EUV into production for its own 7nm process and later extended it into DRAM manufacturing, each time racing to close a gap rather than waiting for further proof. Intel’s comparatively slower EUV transition is widely cited as a contributing factor in the multi-year process delays that cost it its long-held manufacturing leadership — a visible, costly demonstration of what happens to whoever ends up last in this particular race.

That dynamic hasn’t stayed in the past. The same pattern is playing out again right now with High-NA EUV, ASML’s next-generation system: SK Hynix installed its own High-NA tool in September 2025 to prepare for mass production. And Samsung, in spite of financial challenges, is solidly progressing with High-NA EUV. The specific technology has changed. The competitive mechanism hasn’t.

The actual tipping dynamic

What EUV’s adoption history shows isn’t that semiconductor manufacturers stopped being cautious. It’s that caution holds only up to a specific threshold: as long as the perceived cost of adopting something unproven outweighs the perceived cost of falling behind a rival who adopts it first, the conservative choice is to wait. Once that balance flips — once one credible peer moves and starts pulling ahead — the same organizations that spent years being cautious can turn into some of the fastest adopters in the industry, precisely because standing still has become the more expensive option.

What this means for sequencing, not for certainty

None of this means every unproven technology gets this treatment or that any specific process technology today is guaranteed to follow the same arc EUV did — most don’t and betting on inevitability would be its own kind of overclaiming. What it does mean is that the right strategic question for an early-stage supplier in this industry isn’t “how do we convince every conservative customer at once.” It’s closer to “who is the one credible first mover whose adoption would change the calculus for everyone else watching.” That’s a sequencing problem, not a persuasion problem — and it’s the problem EUV’s own history shows has a solvable, well-documented shape, whatever specific technology is running through it next.

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