Field-effect transistors (FETs) are the fundamental building blocks of modern electronics, enabling everything from mobile devices and automotive systems to advanced computing and communications. As semiconductor technology continues to scale toward smaller device geometries and more complex architectures such as FinFETs and gate-all-around (GAAFET) transistors, the sensitivity of devices to atomic-level imperfections has increased dramatically. Even minute levels of contamination or structural disorder at the atomic scale can have measurable effects on transistor performance, reliability and manufacturing yield.

For semiconductor manufacturers, managing atomic-scale defects is becoming a critical challenge that directly affects device economics and long-term product competitiveness.

Why atomic-level defects matter in FETs

Modern FETs operate at nanometer-scale dimensions where device behavior is strongly influenced by surface and interface conditions. Gate oxides, channel interfaces and material layers can be only a few atomic layers thick. At this scale, a single impurity atom or structural irregularity can introduce electrical defects that alter the behavior of the transistor.

One of the most common consequences of atomic-level contamination is increased leakage current. Metallic impurities or atomic defects in gate oxides and interfaces can create unintended conduction paths. This leads to higher off-state leakage currents, which increase standby power consumption and reduce energy efficiency. In applications such as mobile electronics or automotive systems, where low power consumption is critical, even small leakage increases can significantly affect system performance.

Atomic defects also create interface trap states, which capture and release charge carriers at the semiconductor–oxide interface. These traps can cause shifts in the transistor’s threshold voltage (), making device behavior less predictable. Over time, these trap states may also contribute to long-term instability, leading to drift in electrical parameters and reduced device reliability.

Another key effect of atomic-level disorder is carrier mobility degradation. Transistor performance depends on the ability of electrons or holes to move efficiently through the channel. Atomic-scale surface roughness, contamination or lattice disturbances can increase carrier scattering, reducing mobility and lowering drive current. The result is slower switching speeds and reduced circuit performance.

Reliability risks from atomic defects

Beyond immediate performance impacts, atomic defects play a major role in long-term transistor reliability. Several well-known degradation mechanisms are directly linked to atomic-scale imperfections.

For example, time-dependent dielectric breakdown (TDDB) can occur when impurities weaken the gate oxide structure, eventually leading to catastrophic failure. Similarly, bias temperature instability (BTI) is associated with charge trapping in atomic-scale defects at material interfaces, gradually shifting transistor characteristics during operation.

These reliability concerns are especially important in automotive and industrial electronics, where semiconductor devices must operate reliably for more than a decade under harsh environmental conditions.

Manufacturing and yield implications

Atomic-level contamination also presents significant challenges in semiconductor manufacturing. Traditional contamination control systems, including cleanroom filtration and particle inspection tools, are highly effective at controlling micrometer-scale particles but are not designed to address atomic-scale impurities.

Many atomic contaminants originate from materials, process chemicals or equipment surfaces and may be present in concentrations far below the detection limits of conventional metrology tools. Yet these contaminants can still create measurable electrical effects once integrated into device structures.

As a result, atomic-level defects can manifest as parametric variability across wafers, wider electrical distributions and reduced manufacturing yield. Even small variations in defect density may lead to increased binning losses during testing or higher wafer scrap rates.

For high-volume semiconductor production, even a modest improvement in yield—often just a few percent—can translate into substantial financial benefits.

Addressing the root cause: Atomic-Level Purification

Because atomic-scale defects originate from material purity and interface quality, addressing them requires solutions that go beyond conventional cleaning and contamination control methods.

SisuSemi’s Atomic-Level Purification (ALP) technology is designed specifically to target the root causes of atomic defects and contamination. Rather than focusing only on particle removal or surface cleaning, ALP aims to improve material quality at the atomic scale by removing trace contaminants and improving surface atomic ordering.

By reducing atomic impurities and structural disorder, ALP can help decrease defect density in semiconductor materials and interfaces. This can lead to measurable improvements in key device performance indicators, including reduced leakage current, improved threshold voltage stability and tighter parametric distributions.

From a manufacturing perspective, improving atomic-level material quality may translate into higher yield potential and improved reliability margins. In addition, lower leakage currents can contribute to better energy efficiency in end devices, an increasingly important requirement across many semiconductor applications.

A growing industry focus

As semiconductor technology continues to evolve toward smaller device structures and more demanding performance requirements, controlling atomic-scale defects is becoming a central challenge for the industry. Solutions that can address the root causes of contamination and material disorder are likely to play an increasingly important role in enabling future device performance and manufacturing efficiency.

Technologies such as Atomic-Level Purification represent a promising approach to improving semiconductor material quality at its most fundamental level—helping manufacturers unlock new opportunities in device performance, reliability and yield.

The post Atomic-Level Defects in FETs: An Invisible Challenge in Modern Semiconductor Manufacturing appeared first on SisuSemi.

Leakage current is a critical limiter of sensor performance, yield, and reliability. The leakage current is one of the few parameters that directly impacts both yield and product pricing.

Across a typical sensor portfolio, leakage reduction at BEOL can unlock $10–25M annual value.

In this case study, SisuSemi is introducing a new low‑temperature (200 °C) BEOL‑compatible Atomic‑Level Purification (ALP) process that significantly reduces leakage current and variability without violating BEOL thermal budgets.

This BEOL process enables measurable yield recovery, average selling point (ASP) uplift, and reliability improvements across multiple sensor segments.

The Challenge: Leakage Current in Sensor Manufacturing              

Leakage current originates from thermally generated carriers, introducing signal-independent noise and pixel-to-pixel variability that directly impacts sensor accuracy. The problems are visible across the semiconductor sensor landscape. The leakage current is causing:

• Increases electrical noise and degrades signal quality
• Raises power consumption and self‑heating
• Reduces long‑term reliability and device lifetime

For manufacturers, the impact is visible early:

• Test and calibration: higher leakage increases variability and calibration cost
• Yield and binning: leakage‑limited devices are downgraded or scrapped
• Final product quality: residual variability remains even after calibration

Because completed sensor structures are constrained by BEOL thermal budgets, traditional high‑temperature surface treatments are often not viable. This is where SisuSemi’s BEOL process ads value.

The Solution: Low‑Temperature (200 °C) BEOL ALP Process

SisuSemi has developed a BEOL‑compatible ALP process operating at temperatures as low as 200 °C, enabling leakage current reduction on finished sensor devices without risking metal diffusion or structural degradation.

This makes leakage reduction possible where it was previously inaccessible.

Before we look the results, we shall look how this translates to financial impact.

Business Drivers

The Leakage Current has a significant impact across the sensor segments. We have estimated the business impact through Yield-Driven Value and ASP uplift potential.

Yield‑Driven Value (Example Scenario)

Assumptions:

• Annual volume: 10 million sensors
• Current ASP: $2.5 per unit
• Base yield: ~90%
• Leakage‑related yield loss: 2–4%
• Conservative recovery: 75%

Result:

• Yield recovery: 2.25% (3% potential * 75% recovery)
• Saved units: 225 000 annually
• Direct revenue gain: ≈ $0.56M per year

ASP Uplift Potential

A ~50% reduction in leakage current enables re‑binning into higher‑value performance segments. No change in volume.

Example:

• ASP increase from $2.5 → $3.5, uplift +$1.5
• Volume: 10 million units
• Annual revenue upside: ≈ $15M

Estimated Annual Impact by Sensor Segment

Across sensor segments, over 80% of the total value is driven by ASP uplift rather than yield recovery, highlighting the strong link between performance and pricing.

Proven Process Outcomes at 200 °C

SisuSemi validated the low‑temperature ALP process using third‑party commercial sensor components.

Without design‑specific optimization, the following results were demonstrated:

In addition to a 58% median leakage reduction, a 72% reduction in variation (standard deviation) was observed, indicating significantly improved uniformity across devices, directly impacting yield, calibration effort, and final product consistency & performance.

Across a typical sensor portfolio, leakage reduction at BEOL can unlock $10–25M annual value per product line, with the majority driven by ASP uplift rather than yield recovery.
This positions leakage control not just as a process optimization, but as a direct revenue expansion lever.

Why Low Temperature Matters

The key advantage of the 200 °C ALP process is that it enables leakage reduction after BEOL completion, where conventional solutions, using higher temperatures, are no longer viable.
This unlocks performance improvement without redesign, material changes, or front-end process disruption, significantly lowering adoption barriers.

Your Opportunity

Validate 200 °C BEOL‑compatible leakage reduction and performance improvement on your own sensor components using post‑dicing ALP treatment. Initial validation is fast, low risk, and low cost, providing a clear and measurable path to quantify yield improvement, performance gain, and revenue impact on your own products.

About SisuSemi

SisuSemi commercializes decades of academic research into atomic‑level surface and interface purification. Its ALP systems support component‑level and wafer‑level treatment up to 300 mm, improving interfaces by removing atomic‑scale defects (e.g., oxygen, hydrogen, carbon), recovering atomic order, and protecting surfaces with thin crystalline SiO₂.

The post Case Study – Low temperature ALP™ process for Back-End-Of-the-Line (BEOL) sensors. appeared first on SisuSemi.

New BEOL-compatible AtomSeal process unlocks up to $25M annual value per product line for semiconductor sensor manufacturers — without front-end redesign.

SisuSemi (www.sisusemi.com), the leading provider of Atomic Level Purification (ALP) solutions, announced today a significant advancement in its process portfolio: a Back-End-Of-Line (BEOL)-compatible ALP process called AtomSeal, operating at a temperature of 200 °C (about 392 °F). This innovative solution directly addresses one of the most common issues affecting semiconductor manufacturing: leakage current.

Leakage current is a critical limiting factor in terms of yield, reliability and average selling price (ASP) across all types of semiconductor sensors including CMOS image sensors, LiDAR/ToF sensors, MEMS devices, RF/IoT, gas and temperature sensors. Previously, any effort to address this challenge was restricted by BEOL thermal budgets, which limited the application of standard surface treatment techniques that require higher temperatures above 350 °C.

At a temperature of 200 °C, SisuSemi achieved a 58% improvement in leakage current on third-party sensor components and 72% lower leakage current variability (standard deviation).

SisuSemi’s new low-temperature ALP process — validated on third-party commercial sensor components without device-specific optimization — delivered a 58% median reduction in leakage current and a 72% reduction in leakage variability (standard deviation). The drastic decrease in device-to-device variability means a direct improvement in calibration efficiencies, increase in yields, better binning results and enhanced reliability, all achievable post-dicing of the finished sensors.

From the financial standpoint, the effects are significant. For a production of 10 million units of the sensor family, the AtomSeal performance gains may generate an additional $10-$25M of value per year, where more than 80% of the total effect would come from ASP boost through the re-binning to higher-performing segments rather than pure yield gains.

With AtomSeal, we provide a breakthrough solution of atomic-level performance control to the previously ignored part of the manufacturing process. And thus create a tangible revenue generation opportunity for sensor makers.

— Erkki Seppäläinen, CEO, SisuSemi

A key advantage of the AtomSeal process is its low barrier to adoption. Initial validation is fast, low-risk and low-cost, allowing manufacturers to quantify yield improvement, performance gain and revenue impact on their own devices using post-dicing ALP treatment — with no front-end process changes, material substitutions or device redesign required.

The dramatic reduction in device-to-device variation translates directly into improved calibration efficiency, higher yield, better binning outcomes and enhanced long-term reliability — all achievable post-dicing on finished sensor structures.

About SisuSemi

SisuSemi is a Finnish deep-tech company based in Turku, Finland, commercializing decades of academic research from the University of Turku into atomic-level surface and interface purification. Its proprietary ALP technology removes atomic-scale surface defects — including oxygen, hydrogen and carbon contamination — and restores atomic order at semiconductor interfaces. SisuSemi’s systems support component-level and wafer-level treatment up to 300 mm, serving manufacturers across multiple device types, such as sensors, logic, memory, and power device segments.

Media Contact

Markku Lammassaari

CMO, SisuSemi

markku@sisusemi.com

+358400445154

www.sisusemi.com

The post SisuSemi Extends ALP™ Technology to Back-End-Of-Line Processes, Demonstrating 58% Leakage Current Reduction at Temperature of 200 °C appeared first on SisuSemi.

The bridge between these two worlds is often foggy. How exactly does a single misplaced atom in a silicon lattice translate into a missed quarterly shipment or a product recall? To solve this communication gap, we use the atomic defect amplification diagram. This framework provides a clear roadmap from atomic physics to system-level impact, ensuring that everyone from the cleanroom to the boardroom understands the why behind device failure.

1. The root cause: Atomic-level defects

It all starts at the surface. Whether it is surface contamination, a dangling bond, oxide disorder or a simple atomic impurity, these microscopic anomalies are the root causes of chip failure. In a perfect crystal, electrons flow predictably. However, these defects disrupt that harmony, creating the foundation for the cascade that follows.

2. The chain reaction: Interface trap formation

Once an atomic defect is present, it manifests physically as an interface trap. This stage is where the amplification truly begins. These traps lead to:

• Charge trapping: Electrons or holes become stuck, altering the electrical environment.
• Carrier scattering: The physical path of the charge carriers is disrupted, much like a car hitting a pothole on a highway.

These are not just theoretical physics problems; they are the direct precursors to measurable transistor degradation.

3. Transistor-level and device-level impact

As these traps accumulate, the individual transistor begins to struggle. We start seeing increased leakage current, significant threshold voltage () variation and reduced carrier mobility.

At the device level, this translates to:

• Slower switching speeds: The transistor can’t turn on or off as fast as the design requires.
• Increased static power: Even when the device is off, it’s still bleeding energy.
• Reliability degradation: The device effectively ages faster than intended.

4. The macro scale: Chip and system consequences

When millions—or billions—of these compromised transistors are packed onto a single die, the problem scales exponentially. We no longer talk about traps; we talk about thermal hotspots, reduced performance and yield loss.

By the time the silicon reaches the system level (your smartphone or a server farm), the defect has amplified into:

• Thermal throttling: The system must slow down to avoid melting itself.
• Reduced energy efficiency: Battery life drops or data center cooling costs skyrocket.
• Reliability failures: The dreaded Blue Screen or hardware bricking that ruins a brand’s reputation.

5. The bottom line: Business impact

For the C-suite, the atomic defect amplification diagram concludes with a sobering reality check. Atomic-scale issues directly dictate:

• Lower yield: Fewer functional chips per wafer means higher costs per unit.
• Higher power budgets: Products that can’t meet green energy standards or mobile battery requirements.
• Reduced competitiveness: A product that is slower, hotter and less reliable than the competition is a product that doesn’t sell.

Summary: Connecting the dots

The power of this diagram lies in its ability to connect atomic physics → device physics → chip behavior → system impact. It reminds us that in the semiconductor world, there is no such thing as a small problem. Every system-level failure can be traced back to an atomic-level cause, and every atomic-level improvement has the potential to save millions in yield loss.

So in short: How do atomic defects in semiconductors cause business failures?

Atomic defects create interface traps that increase leakage, degrade transistor performance, and reduce reliability. When scaled across billions of devices, these effects lead to lower yield, higher power consumption, thermal throttling, and product failures—directly impacting cost, competitiveness, and brand reputation.

The post The Butterfly Effect of Silicon: How Atomic Defects Drive Business Failures appeared first on SisuSemi.

For semiconductor professionals, the battle for yield has always been fought at ever-shrinking scales. But since the turn of the millennium, we have entered a new era: the atomic battlefield. Defects are no longer just killer particles; they are misplaced atoms, lattice vacancies and interfacial contamination measuring less than a nanometer.

As we scale towards 2nm and beyond, the tolerance for these atomic-level imperfections has evaporated. While the industry has made heroic strides in detecting these flaws, detecting a killer is not the same as neutralizing it. This blog explores the exponential growth of the atomic defect detection market, the insurmountable limits of traditional tackling strategies, and the emerging frontier of Atomic-Level Purification (ALP) as the essential partner to detection.

The nanoscale detection explosion (2000 – present)

Since 2000, the semiconductor defect inspection and metrology market has grown from a necessary back-end checkpoint into a front-end, process-critical powerhouse. While specific atomic-level subsets are harder to segment, the broader semiconductor defect inspection equipment market—which includes tools capable of nanoscale resolution—reflects this trend. According to Fortune Business Insights, valued at roughly 6.14 B USD in 2025, it is projected to surpass 13.4 B USD by 2034, growing at a CAGR of 9.03%.

This explosive growth is driven by three factors:

1. Node Scaling: Transitioning from 130nm in 2000 to sub-3nm today means a defect that was negligible ten years ago is now a device-killing monster.
2. 3D Architectures: The move from planar transistors to FinFETs, Gate-All-Around (GAA), and 3D NAND has created complex, high-aspect-ratio trenches and buried interfaces where atomic defects can hide from conventional line-of-sight inspection.
3. The EUV Revolution: Extreme Ultraviolet (EUV) lithography enables tighter patterning but introduces stochastic defects—random photon noise that causes line-edge roughness, missing contacts or bridges at the atomic scale.

To combat these, a new arsenal of detection solutions has emerged, including Multi-Beam Electron Beam (e-beam) inspection for throughput-sensitive nanoscale scanning, Actinic EUV Mask Inspection to see defects “in the same light” they print and the integration of AI/ML to classify anomalies from massive metrology datasets. Concurrently, material science has advanced our theoretical understanding of point defects, dislocations and stacking faults in novel materials like SiC, GaN, and 2D semiconductors.

The limits of currently utilized solution: Standard fixes fall short

Detecting an atomic-level defect is vital, but how does a fab currently tackle one? The short answer is: they try to prevent them through massive investments in cleanrooms and process optimization, or they try to wash them away. However, standard solutions do not resolve the root causes of atomic-level defects, they just try to live with them. Thus, they face critical shortcomings in the atomic realm:

• Standard wet/dry cleaning: RCA and Piranha cleans are designed to remove particles and organic contaminants. They are blunt instruments that cannot precisely targeted single-atom impurities or native oxides without disrupting the delicate crystallinity of the underlying substrate. They often leave disordered surface layers.
• Process control feedback: Advanced Process Control (APC), often enhanced with AI technologies, can adjust lithography or etch parameters to mitigate the impact of defects, but it cannot remove them. It acts as a palliative care system for a wafer that is fundamentally sick at the lattice level.
• The yield tunnel: Manufacturers are forced to accept lower yields or run more inspection-repair loops, crippling throughput and blowing up the cost-per-die. We are hitting a wall where inspection throughput cannot keep pace with scaling complexity.

The missing piece: SisuSemi Atomic-Level Purification (ALP)

To break through this wall, the industry must transition from defect management to defect eradication. This requires Atomic-Level Purification (ALP) technologies that work alongside advanced detection systems.

SisuSemi ALP solution, rooted in deep material science, targets the root cause of interface failures. Their proprietary process uses low-temperature Ultra-High Vacuum (LT-UHV) treatments to:

1. Eradicate atomic contaminants: Selectively remove individual-atom impurities, such as carbon, from the substrate surface.
2. Restore crystallinity: Enhance the crystalline order of the semiconductor substrate surface.
3. Suppress interfacial disarray: Prevent the formation of amorphous or disordered native oxides that introduce trap states and increase leakage current, by forming a thin, protective, crystalline SiO₂ layer.

By pairing SisuSemi ALP with atomic-level detection, manufacturers can e.g. reduce chip power consumption, enhance breakdown voltages in power devices and ensure the reliability of quantum computer components.

The growth of Atomic-Level Purification is not optional; it is a necessity. For semiconductor professionals aiming at the 2nm frontier, the message is clear: You cannot build a perfect house on a shaky foundation. Detection shows you where the foundation is broken; SisuSemi ALP ensures you start with a perfect surface.

The post The Atomic Battlefield: Why Detection Alone Won’t Save Next-Gen Yields appeared first on SisuSemi.

For CMOS imaging sensor (CIS) manufacturers, atomic-scale contamination is no longer a background variable — it is a primary driver of yield loss, noise performance and product reliability.

CMOS image sensors have become one of the most defect-sensitive device categories in semiconductor manufacturing. Every pixel in a CIS die must convert photons to electrons with consistent efficiency, negligible leakage, and stable behaviour over the product’s lifetime. That demands near-perfect material interfaces at scales where a single misplaced atom can degrade an entire pixel. As resolutions climb past 200 megapixels, pixels shrink below 1 µm, and automotive qualification standards tighten, atomic-level contamination has moved to the centre of the yield and quality challenge for CIS vendors.

How atomic defects degrade imaging performance

The most consequential defect-driven failure mode in CIS is dark current: unwanted charge generated in a pixel even in complete darkness. Metallic contamination — trace quantities of iron, copper or nickel from process equipment or chemicals — introduces deep-level trap states in silicon and at the silicon–oxide interface. These traps generate electron-hole pairs thermally, producing a baseline signal that raises noise, reduces the signal-to-noise ratio and directly limits low-light sensitivity. In night photography, scientific imaging and automotive vision systems, even modest dark current increases translate into visible image degradation.

The same defect states that generate dark current also act as recombination centres, capturing photo-generated carriers before they reach the readout circuitry. The result is reduced quantum efficiency and a compressed dynamic range — both critical metrics in high-end consumer, medical and machine vision applications.

Charge trapping and detrapping at defect sites also contributes to temporal noise and fixed pattern noise (FPN). FPN, which arises from pixel-to-pixel variation in defect density across the sensor array, is particularly damaging because it cannot be eliminated by simple averaging and requires complex correction algorithms that add latency and system cost.

The yield and reliability consequences for CIS vendors

For CIS manufacturers, these physics-level effects translate into hard commercial consequences. A 200-megapixel sensor die contains upwards of 2 × 10⁸ individual photodiodes. Even an apparently negligible defect density can produce hundreds of hot pixels per die — permanently bright or dark pixels caused by localised defect states generating continuous leakage — which are detected at wafer test and trigger bin-out. The larger the die and the higher the resolution, the more unforgiving this arithmetic becomes.

Reliability presents an equally demanding challenge. Charge trapping in pixel gate oxides, interface degradation in photodiodes, and dielectric breakdown driven by metallic contamination all cause sensor performance to drift over time: rising noise floors, increasing pixel failure rates, and calibration instability. For automotive imaging applications, where sensors must meet AEC-Q100 qualification and operate reliably across a 15-year vehicle lifetime under thermal and electrical stress, this is not an acceptable failure mode. It is a disqualifying one.

Advanced Backside Illuminated (BSI) architectures compound the difficulty. Backside-illuminated sensors require thinning the silicon substrate to a few micrometres and forming a high-quality passivation layer on the exposed backside surface. This interface is inherently more challenging to control than the front surface and is acutely sensitive to contamination introduced during thinning, passivation deposition and any subsequent thermal steps. Inadequate backside passivation is a leading cause of elevated dark current in BSI sensors and a persistent yield limiter for manufacturers at the leading edge.

Where conventional cleaning falls short

Standard wet cleaning sequences — RCA clean, dilute HF, ozone-based chemistries — were engineered for defect scales and process tolerances from previous technology generations. They are effective at removing particulate contamination and bulk chemical residues, but they were not designed to eliminate sub-monolayer metallic contamination or to control interface bond configuration at the atomic level. At today’s pixel dimensions and dielectric thicknesses, that gap is consequential. Conventional cleans leave residual contamination that is invisible to standard metrology but fully capable of generating the dark current and interface trap densities that drive yield loss.

Atomic-Level Purification: A purpose-built solution

SisuSemi’s Atomic-Level Purification technology addresses these limitations directly. Designed from the ground up to operate at the atomic scale, it removes individual contaminant atoms and controls surface bond termination with a precision that bulk-phase cleaning chemistry cannot match. The practical outcomes for CIS manufacturing are measurable and direct:

• Metallic contamination is reduced below the threshold at which deep-level traps form, directly suppressing dark current generation and pixel defect rates.
• Atomic-scale control of interface termination enables passivation and dielectric layers to be deposited onto surfaces with substantially lower interface trap densities, improving quantum efficiency and reducing FPN.
• Cleaner BSI backside surfaces support more effective passivation, addressing one of the most persistent dark current sources in advanced sensor architectures.
• The technology integrates into existing CMOS process flows without requiring wholesale fab infrastructure changes, and can be applied selectively at the steps where surface cleanliness has the greatest impact — prior to gate dielectric deposition, before passivation on BSI backsides, and ahead of ALD processes on high-aspect-ratio pixel structures.

 As CIS pixel dimensions continue to shrink and resolution requirements push further upward, the margin for atomic-level imperfection approaches zero. For vendors competing on sensor noise performance, yield efficiency, and automotive-grade reliability, surface purity at the atomic scale is no longer an aspirational target — it is a manufacturing requirement. SisuSemi’s Atomic-Level Purification is built precisely to meet it.

The post Atomic-Level Defects in CMOS Image Sensors: The Hidden Cost of Impurity appeared first on SisuSemi.

In this post, we’ll unpack what these challenges are, why they matter deeply during lithography, and how they ripple through to impact chip performance, quality and manufacturing yield.

Understanding the challenge: Atomic-level defects and contamination

At the heart of semiconductor fabrication are layer upon layer of precisely engineered materials. Between these layers, interfaces form boundaries where different materials meet. Ideally, these interfaces should be perfectly clean and structurally sound. But reality is something else.

Atomic-level defects (like vacancies, dislocations or interstitial atoms) and contamination (such as trace metals, organic residues or unwanted particles) often emerge during material deposition, etching or even during wafer handling. While these imperfections might seem insignificant, they become critical when the target features on the chip are only a few nanometers wide.

How these issues affect the lithography process

Lithography is the process of transferring intricate circuit patterns onto a semiconductor wafer using light (or in EUV lithography, extreme ultraviolet radiation). Here’s how atomic-level defects and contamination wreak havoc in this phase:

1. Pattern distortion & line edge roughness (LER):
   Contaminants and surface defects scatter light unpredictably during exposure. This scattering causes distortions in the printed features, leading to line edge roughness and pattern fidelity issues. These defects increase variability and degrade the precision of critical dimensions (CD).
2. Photoresist adhesion failures:
   Clean, defect-free interfaces are crucial for photoresist to adhere properly. Atomic-level contamination reduces surface energy uniformity, leading to adhesion failures, resist lift-off or incomplete pattern transfer.
3. Focus and overlay errors:
   Surface topography changes caused by defects can affect the planarization of the wafer. Uneven surfaces make it harder to maintain focus and alignment between layers — critical for multi-patterning techniques used in advanced nodes.
4. Chemical amplification variability:
   In chemically amplified resists (CARs), surface defects can locally interfere with the acid-catalyzed reactions that define the pattern. This results in uneven exposure and development, further degrading pattern integrity.

Impact on performance, quality and yield

The implications of these lithography-related issues are significant:

• Performance degradation:
  Inconsistent patterning leads to variability in transistor dimensions. Since electrical performance is highly sensitive to geometry at nanoscale, even minute deviations can cause slower switching speeds, increased leakage currents and overall degraded chip performance.
• Yield loss:
  Wafer defects that propagate through lithography often result in functional failures of the final devices. With defect density targets approaching near-zero at advanced nodes, even a small increase in lithography-induced defects can translate to significant yield losses.
• Reliability concerns:
  Chips that pass initial testing but have marginal patterns due to surface defects may fail prematurely in the field. This reliability risk is unacceptable for applications like automotive, aerospace and critical data center environments.
• Escalating costs:
  Low yield drives up the cost per good die, especially as fabs run multi-billion-dollar EUV tools. Reworking wafers is costly and time-consuming, and scrapped wafers represent a direct loss.

Existing mitigation strategies

The semiconductor industry is attacking this problem from multiple angles:

• Advanced cleaning and surface preparation:
  Atomic-level cleaning techniques, such as cryogenic CO₂ cleaning and advanced plasma treatments, are being adopted to reduce surface contaminants.
• Defect inspection and metrology:
  New generations of high-resolution inspection tools capable of detecting atomic-scale anomalies before lithography are critical for defect control.
• Materials engineering:
  Developing new photoresists and underlayer materials that are less sensitive to surface defects helps improve pattern fidelity.
• Process control and automation:
  Real-time monitoring and AI-driven process adjustments help catch and correct issues before they affect yield.

However, each of these methods comes with its own set of limitations. Furthermore, they are not able to tackle the root causes of atomic-level defects and contamination.

The SisuSemi Atomic-Level Purification: A superior solution for lithography

SisuSemi Atomic-Level Purification (ALP) takes a unique approach to silicon surface cleaning and treatment, leveraging an advanced technique that combines Ultra High Vacuum (UHV), elevated temperatures (< 450°C) and controlled oxidation.

The UHV environment ensures that the silicon surface is exposed to minimal contaminants during the cleaning process, eliminating airborne particles and chemical impurities that could compromise the integrity of the silicon. UHV allows for precise control of atomic interactions, ensuring that the silicon surface is thoroughly cleaned without introducing additional defects.

By heating the silicon to controlled temperatures under UHV conditions, the surface atoms are able to move and reorganize, helping to restore the crystalline structure. This process helps eliminate dislocations and vacancies, leading to improved material properties.

A very thin and controlled layer of silicon dioxide (SiO2) is formed on the silicon surface. This layer acts as a protective barrier, preventing further contamination and providing a stable foundation for additional processing steps.

Conclusion

As the industry marches deeper into the atomic scale, the battle against atomic-level defects and contamination at semiconductor interfaces has become front and center — especially in the lithography phase. These seemingly invisible adversaries can derail the immense precision required to produce today’s cutting-edge chips.

For fabs, equipment makers, and material suppliers alike, maintaining hyper-clean, defect-free surfaces isn’t just about good practice — it’s about survival in the era of atomic-scale manufacturing.

By utilizing novel technologies such as SisuSemi Atomic-Level Purification, lithography processes can be successfully employed to advanced process nodes and to better chip performance, quality and manufacturing yield.

The post The Hidden Threat: How Atomic-Level Defects and Contamination Challenge Lithography in Semiconductor Fabrication appeared first on SisuSemi.

SisuSemi has partnered with IPG Photonics, the world leader of fiber laser technology, to introduce a breakthrough Ultra‑High‑Vacuum (UHV) wafer cleaning system that pairs atomic‑level cleanliness with a first‑of‑its‑kind laser‑based wafer heating technology. The system supports wafer sizes up to Ø300 mm, with full flexibility to process Ø200 mm and Ø150 mm wafers, unlocking new levels of wafer purity for the most advanced semiconductor nodes. This solution is part of SisuSemi’s ALP (Atomic‑Level Purification) technology platform, engineered to deliver unmatched wafer surface quality for advanced semiconductor manufacturing.

Uniform wafer heating is foundational to many semiconductor manufacturing technologies.

With the SisuSemi’s patented ALP solution – using uniform heating, UHV and controlled oxidation – the solution directly addresses one of the most critical bottlenecks in the semiconductor industry: surface and interface defects and contaminants. In advanced nodes, interface contamination and defect density are among the primary causes of leakage current, threshold voltage instability, and yield loss. As devices move towards smaller node sizes, traditional cleaning and thermal treatments can no longer ensure the atomic‑level surface quality required for reliable device performance. A remote laser heating solution enables contamination control because the laser beam delivery optics are outside the UHV process chamber.

When designing its next‑generation UHV cleaning platform – called AtomSeal – SisuSemi evaluated multiple heating methods before selecting laser heating based on its attributes for uniformity, repeatability, and throughput scalability.

SisuSemi’s CTO Elmira Jahanshah Rad: “When we designed our wafer solutions, we weighed traditional resistive heating and laser heating. Laser heating provides uniformity and throughput scalability that are crucial for scaling SisuSemi solution to large volume manufacturing”.

IPG Photonics’ laser heating system delivers highly uniform heating across the full Ø300 mm wafer area, the global industry standard. Combined with SisuSemi’s ALP UHV cleaning process, we can now support state-of-the-art R&D and low volume fabs with atomic-level cleanliness in semiconductor industry for wafer sizes up to Ø300 mm. Fiber delivery allows the laser’s power unit and utilities to be positioned outside the cleanroom. Only the optical head at the distal end of the fiber delivery is near the process chamber, saving valuable cleanroom space while simplifying equipment integration and service.

The AtomSeal complete system is now commissioned in SisuSemi cleanroom, able to serve Front-End-of-Line processes for foundries and IDMs working on advanced CMOS, photonics, and MEMS — especially 3 nm and below — targeting applications in edge computing, IoT, AI, and high-frequency devices. The ALP process is also applicable to conventional technologies, where atomic-level cleanliness can reduce power consumption and increase production yield. The ability of laser to uniformly heat over a large area multiplies the treatment capacity of diced chips in the Back-End-of-Line to deliver side wall passivation directed at reducing leakage current and dicing induced yield losses, providing proven benefits for sensors and detectors.

SisuSemi’s roadmap includes scaling ALP to high‑volume manufacturing tools with seamless integration into 300 mm production lines. This and future generations of SisuSemi’s AtomSeal systems are engineered to fit into existing fabs as either pre‑ or post‑treatment steps, without breaking vacuum.

Andrey Mashkin, Vice President, GM Global Lasers: “Combining our laser heating solution with SisuSemi’s UHV based atomic-level cleaning enables new standards in wafer quality while accelerating IPG’s vision for the sustainable Fab. Laser heating is fast, clean and efficient, with minimal service and consumable requirements.”

SisuSemi CEO Erkki Seppäläinen: “This partnership transforms how fabs approach wafer cleanliness — beyond conventional limits.”

About SisuSemi Oy:

Founded in 2024 and based in Turku, Finland, SisuSemi Oy specializes in silicon-based semiconductor surface cleaning at the atomic level. Leveraging over 10 years of research from the University of Turku, SisuSemi is dedicated to improving chip quality and performance through innovative and sustainable technology solutions that empower manufacturers to push the boundaries of performance.

For more information, see SisuSemi web page: www.SisuSemi.com  

Erkki Seppäläinen

CEO, Co-founder, SisuSemi 

erkki@sisusemi.com 

+358 40 7687591

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That layer is the silicon oxide interface between the transistor and the rest of the device. And today, most of the industry still relies on chemically grown oxide, which comes with inherent problems:

• it traps unwanted charge,
• leaks more current than expected,
• and weakens long‑term reliability.

The SiO2 quality issues plays bigger role as companies move to new transistor designs like Gate‑All‑Around nanosheets and to stacked 3D chip architectures where traditional high‑temperature fixes are no longer possible.

Companies have tried workarounds – special anneals, nitrogen treatments, and plasma steps – but these often introduce new reliability risks or demand temperatures that advanced manufacturing flows cannot tolerate.

Real Business Impacts

Poor interface quality affects the three things that most influence revenue:

1. Product performance

Defects in chemical oxides reduce drive current and limit how aggressively a company can tune for speed.
Higher electric fields in new transistor architectures amplify these weaknesses.  

2. Power and energy efficiency

Chemical oxides leak more current than their thickness suggests. This forces higher guard bands and increases power consumption, directly impacting data‑centre operating cost and battery life.

3. Yield and long‑term reliability

Unwanted charge in the oxide shifts transistor behaviour over time, causing failures and yield loss. In advanced nodes, even a small shift in yield becomes expensive.

What the latest research shows

Global research leaders have demonstrated that if you improve SiO2 and interface quality, by reducing hydrogen‑related defects and avoid trapped charge from the start, you can produce a cleaner, stable oxide layer at low temperature – outperforming even the best traditional high‑temperature oxides.

This proves the point: the problem is in the quality of oxide and in the interface.

SisuSemi changes the game

SisuSemi uses a fundamentally different approach.

Ultra‑high vacuum + controlled, low‑temperature oxidation

This method removes atomic‑level contaminants before oxide growth and produces an exceptionally clean and orderly interface.

The result: far fewer defects, lower leakage, and dramatically improved reliability – all at temperatures compatible with next‑generation chip designs.

Why customers care

• Lower power at the same performance
• Higher performance at the same power
• Reduced variation and higher yield
• Compatibility with stacked 3D and future transistor architectures

Across early test structures, SisuSemi’s process has delivered large reductions in leakage and significant reductions in interface defects, directly improving both performance and reliability.

What this means for your roadmap

If your company is moving toward:

• New transistor designs (e.g., Gate‑All‑Around)
• Stacked 3D logic
• Continued voltage scaling
• More aggressive power targets

…then oxide quality becomes a business‑critical differentiator, not just a technical detail.

The companies that fix this interface now will enjoy higher margins, better yield, lower power, and smoother node transitions.

Next step

We recommend a fast evaluation on your process flow, comparing your current oxide with SisuSemi’s low‑temperature interface treatment. The test is straightforward, low‑risk, and produces measurable results in few weeks.

The post Chemical SiO2 – The Hidden Weak Link in Advanced Chips appeared first on SisuSemi.

This article explains what leakage current is, why it arises, and most crucially how surface quality and interface defect control can be leveraged to reduce leakage current in advanced semiconductor devices.

What Is Leakage Current and Why It Matters

In semiconductor devices, leakage current refers to unintended current flow when a device should ideally be non-conductive, so called off-stage. In practice, this can appear as off-state current in transistors, reverse bias leakage in diodes, or parasitic current paths that detract from intended operation. At smaller nodes, leakage current can rise to levels that meaningfully affect static power and noise margins even in digital logic, and more so in analog, memory, and sensor circuits.

Industry has been reporting from low yield due to leakage current as well as from delayed technology adaptation due to increased leakage current. These reports are emphasizing how important the leakage current management is.  The table below summaries the key business consequences.

Leakage current also correlates with reliability and heat generation: increased leakage tends to increase power dissipation and accelerate degradation mechanisms in semiconductor packages. In memory devices, sustained leakage under stress can degrade oxide layers and hasten failure mechanisms.

Business Impact from Leakage Current

It’s important to understand that reducing leakage current by 50%+ is not just a technical achievement. It delivers measurable business value as well.

For advanced semiconductor nodes, even a modest leakage reduction can improve manufacturing yield by 3–5%, translating into millions of dollars in cost savings per production run.

Lower leakage also reduces static power consumption, enabling energy-efficient designs that meet stringent market requirements for AI, automotive, and IoT applications.  

Beyond the cost, the improved reliability minimizes warranty risks and smaller leakage current in chips accelerates time-to-market, giving manufacturers a competitive edge in high-growth segments. Companies that master leakage control will lead in energy efficiency and reliability – critical differentiators in next-gen semiconductor markets.

In short, mastering leakage control is a direct lever for profitability, sustainability, and market leadership.

Root Causes: Atomic-Level Defects and Interface Trap States

A central insight in leakage current physics is that unwanted currents often arise from localized defect states within or adjacent to critical interfaces within a semiconductor device. These defect states can exist in dielectric materials, at interfaces between silicon and oxides, or around contamination sites left from imperfect processing.

Atomic-level defects and contaminants create mid-gap trap states at surfaces and interfaces, interfering with charge transport and increasing leakage currents and power consumption.

More specifically:

• Defect states near the semiconductor/insulator interface act as stepping stones that enable carriers to traverse what should be an insulating barrier.
• These trap states increase leakage conduction paths and reduce effective isolation.
• Variability in defect densities contributes to variability in device leakage and reliability performance.

External first-principles studies corroborate this mechanism: theoretical work on the Si/SiO₂ interface shows that even a small number of dangling bonds and interface defects can increase leakage current by hundreds of times  compared to defect-free interfaces.

How Interface Defect Density Drives Leakage

In advanced devices, e.g. GAA, CMOS, memory, and sensor, leakage mechanisms include subthreshold leakage, gate-oxide tunnelling, trap-assisted tunnelling, and stress-induced leakage due to charge trapping at defect sites. Defects can also introduce variability and noise, further impacting performance in sensitive analog or RF circuits.

Interface defect density (often termed Dit) is a key driver of device leakage. High Dit increases trap-assisted conduction pathways and undermines threshold stability and isolation. 

Strategies for Reducing Leakage Current

To effectively reduce leakage current in advanced devices, it is necessary to address both device physics and material/process quality factors that contribute to leakage.

1. Minimize Interface Defects Through Advanced Surface Preparation

Improving surface quality at the atomic level reduces the density of defects that give rise to trap-assisted leakage. SisuSemi’s research and solution approach leverage atomic-level surface cleaning techniques that have demonstrated measurable improvements in electrical performance, including reduced leakage current and lower defect density in advanced nodes. 

Improving surface cleaning can be complementary to process steps such as atomic layer deposition (ALD) of gate dielectrics and controlled oxidation to form high-quality crystalline or near-crystalline interface layers, which have lower trap densities than poorly ordered oxides. 

2. Passivation of Trap States

Passivation techniques, including hydrogen termination and controlled pre-oxide treatments, can neutralize active trap sites at the silicon/dielectric interface, reducing their ability to support leakage pathways. Studies on silicon oxide passivation show that such treatments can significantly lower interface defect densities and concomitantly reduce leakage current in photodiodes and similar structures. 

3. Controlled Process Integration

Integrating cleaning, passivation, and interface formation steps in a controlled environment – such as ultra-high vacuum or tightly regulated oxidation sequences – can maximize the quality of critical interfaces and prevent recontamination that would otherwise increase leakage. SisuSemi’s advanced surface treatment technology has been successfully applied to MOS capacitors, photodetectors, and p-n diodes, yielding leakage current reductions between roughly 50% and 75% in these components.

Measurable Impact: Case Study Results

Leakage current is not fixed by material and chip design – it’s also driven by the interface quality and atomic level cleanliness. Our Case Studies shows how leakage current can be reduced with commercial components:

• MOS capacitors treated with advanced interface preparation exhibited 67% lower leakage current and a 42% reduction in interface defect density. 
• Photodetectors saw ~50% leakage reduction, improving detection sensitivity and noise performance. 
• p–n diodes experienced up to a 75% decrease in leakage, enhancing stability in extreme environments. 
• Radiation Detector Sensors experienced up to 80% reduction in leakage and up-to 75% variation reduction, leading to lower calibration cost and more stable product performance.

These improvements not only reduce static power and error rates but also improve manufacturing yield and reliability, enabling devices to meet stricter performance and quality requirements.

Conclusion: Leakage Reduction Begins at the Interface

Reducing leakage current in advanced semiconductor devices is not solely a matter of circuit optimization; it is fundamentally tied to material quality at the atomic scale. Defects and contaminants at critical interfaces create trap states that enable unintended current paths and increase power consumption. Through improved surface preparation, defect passivation, and tightly controlled process integration, manufacturers can substantially reduce leakage paths, improve energy efficiency, and enhance device performance.

As device geometries continue to shrink and performance demands increase, mastering leakage current reduction through interface control will be essential to sustaining innovation and competitiveness in semiconductor technology. SisuSemi offers one solution to enable the cleanest interfaces that leads to smallest leakage currents. Reach out to learn more.

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