Addressing Damage in Diced Sidewalls Prior to Packaging

In the world of semiconductors, ensuring that current flows precisely through the active area is essential.

But what happens when it leaks through the edges? This common issue can significantly impact performance and reliability.

Generally, leakage current in semiconductors arises from multiple sources:

·       Defects in the insulator

·       Free electrons/holes at the surface and interface due to existing defects and lack of passivation

·       Defects caused by the edges of the component during the dicing process

For example, H. Xia et al. in their study "Sidewall Chipping Investigation & Challenges on 100um Thin Low-K Wafer with DAF" (https://ieeexplore.ieee.org/document/10492406) have explored wide range of process settings to minimize the chipping defects at the sidewalls.

The leakage current introduced at diced sidewalls could be reduced by expensive dicing solutions like plasma dicing, or by heavy optimization of dicing process itself. However, achieving a diced sidewall with near zero chipping remains still as a challenging target.

Additionally, even without chipping, the sidewall is exposed to contaminants and lacks a passivation layer to minimize leakage current. In other words, the perfectly diced sidewall is still a source for a leakage current.

Novel Solution

Another approach to address this issue is to introduce atomic-level cleaning and passivation process that helps reduce leakage current through diced sidewalls. 

SisuSemi’s solutions are perfect for this purpose. Besides cleaning & passivating the diced sidewalls, the process also helps to reduce atomic-level defects under the existing insulator surfaces.

With SisuSemi's treatment for diced components, we have demonstrated significant improvements in leakage currents.

While this blog focuses on leakage current introduced at diced sidewalls, it's important to note that SisuSemi’s solutions also tackle other leakage current sources.

When this process is applied, for example after dry etching, it helps to clean the surface from contaminants and re-order the atomic-level structure and increase smoothness. Additionally, we can grow a thin crystalline SiO2 layer that passivates the surface with minimal defects that could cause leakage current.

This is the beauty of SisuSemi’s solution. It does offer a versatile tool that can be utilized in multiple steps, solving several issues related to atomic-level cleanliness.

With this solution, you can achieve lower power consumption, higher yield, and longer product lifetime, all supporting the sustainability of your product.

Want to learn how SisuSemi can revolutionize your semiconductor manufacturing? Contact us today to discover more about our innovative solutions!