Atomic Layer Deposition has earned its place as the workhorse of advanced-node manufacturing. Its self-limiting, layer-by-layer chemistry gives fabs something no other deposition method can match: Ångström-level thickness control and near-perfect conformality across the most complex 3D structures — nanosheet channels, high-aspect-ratio contacts and DRAM capacitor stacks. But ALD’s precision rests on an assumption that is rarely examined closely enough: that the surface it lands on is clean, chemically uniform and structurally ordered. Increasingly, that assumption doesn’t hold — and the gap between what ALD is capable of and what it actually delivers is being decided before the ALD chamber door even closes.

The overlooked variable: What’s already on the surface

ALD chemistry depends on a predictable population of reactive surface sites — hydroxyl groups, dangling bonds in known locations, a lattice that behaves the way the recipe expects. In practice, wafers rarely arrive at the ALD step in that ideal state. Prior wet cleans, plasma etch and implant steps leave behind residual carbon and hydrogen-related fragments, native oxide regrowth, surface roughness and disordered near-surface lattice structure. Research on wet-processed silicon has shown that HF/RCA-type sequences can leave dangling bonds and elevated surface roughness that compromise subsequent epitaxy and interface quality, while plasma-based cleans, though effective at removing residues, can leave halogen species behind and introduce new sub-surface damage of their own. Neither step fully resolves the atomic-scale disorder sitting just beneath the visible surface.

That residual contamination is not be omitted once ALD begins. Independent nucleation studies have repeatedly shown that surface termination and residual chemistry govern how — and how well — an ALD film nucleates: contaminated or chemically mismatched starting surfaces produce nucleation delay and island-style growth instead of uniform layer-by-layer growth, sometimes requiring tens to hundreds of extra cycles before continuous film coverage is even reached. The result is thickness non-uniformity, pinholes and elevated interface trap density (Dit) at the boundary between the new film and the silicon beneath it. Even in advanced DRAM gate stacks, ALD oxide films have been shown to retain unexpected defects and elevated Dit that trace back to the interface they were grown on, not the deposition chemistry itself.

This matters more with every node shrink. In gate-all-around nanosheet transistors at 2–3 nm, the gate wraps the channel on every side, dramatically increasing the surface-to-volume ratio of the active region, and interface trap states now directly influence leakage and device-to-device variability. Interface quality, once a secondary concern behind geometry, has become a first-order limiter of leakage, variability, and yield. Put simply: ALD can only be as good as the surface it is asked to build on.

From atomic defects to business losses

The consequences of an imperfect starting surface don’t stay confined to a lab notebook — they show up on the balance sheet.

Yield. At advanced nodes, yield is extraordinarily sensitive to defect density, and the industry’s own capital spending confirms it: the market for advanced-node wafer defect inspection systems is forecast to grow from roughly 3.0 B$ in 2026 to nearly 8.9 B$ by 2036, as fabs push from statistical sampling toward comprehensive inline inspection specifically to catch nanoscale defects before they propagate through increasingly expensive process steps.

Wafer economics. Those expensive process steps are not abstract. Leading-edge 3nm-class wafers now run in the neighborhood of 17,000–22,000 $ each, and TSMC’s advanced-node portfolio — 7nm and beyond — accounts for roughly three-quarters of its wafer revenue amid surging AI-driven demand and continued price increases. A defect introduced before deposition that later causes a die, a lot, or a qualification cycle to be scrapped is an expensive loss at those price points, and capacity itself is constrained enough that the opportunity cost of a wasted wafer is compounding.

Power and performance. Interface traps and defect-assisted conduction paths drive up subthreshold leakage and static power. For battery-powered and edge devices, that translates directly into reduced runtime and tighter thermal margins — exactly the specifications customers scrutinize hardest.

Reliability and field risk. Variability introduced at the interface propagates into device-to-device spread, threshold voltage drift, and calibration overhead, which can mean costly post-production calibration or elevated field-failure rates in sensor and precision-analog applications.

In short, atomic-level surface defects that predate the ALD step don’t just cause a materials-science curiosity — they erode yield, inflate power budgets, and slow time-to-market at the exact moment the industry can least afford it.

Fixing the surface before ALD ever starts

This is precisely the gap that novel pre-deposition surface engineering approaches are now targeting — and SisuSemi’s ALP (Atomic Level Purification) is a leading example of that category. ALP is not another cleaning step bolted onto the existing wet-clean-plus-plasma sequence. It is an ultra-high-vacuum, temperature-controlled purification and stabilization process applied upstream of ALD, designed to reset the silicon surface to a genuinely low-defect baseline.

Applied before the ALD step, ALP works on three fronts. It removes embedded atomic-scale contamination — carbon and hydrogen-related species that conventional wet and plasma cleans struggle to eliminate without damaging the surface. It repairs and reorders the near-surface lattice, suppressing the defect-mediated leakage paths that show up later as elevated Dit. And it forms a thin, controlled passivating layer that preserves that clean, ordered state until the wafer reaches the ALD chamber — so nucleation begins on a surface the recipe was actually designed for.

The downstream effect is a more predictable ALD process: more uniform nucleation, fewer pinholes, and dielectric films that behave the way the process specification intends. Outcomes from applying atomic-level purification ahead of deposition include a 3–4x reduction in defect density, leakage current cuts of up to 70%, up to a 20% increase in manufacturing yield, and as much as a 50% improvement in battery life for end devices — figures that translate directly into the yield and power metrics fabs are under the most pressure to improve.

Crucially, this kind of solution is complementary rather than competitive with ALD — it doesn’t replace deposition or etch tooling, it makes them more effective, and it is designed to integrate into existing production lines without major disruption.

The takeaway

As transistor architectures push past the point where geometry alone can save them, the industry’s remaining performance headroom increasingly lives at the atomic scale — in the handful of surface layers ALD builds on top of. Treating pre-ALD surface preparation with the same rigor as the deposition step itself isn’t a nice-to-have refinement anymore. It’s fast becoming a prerequisite for getting the yield, power, and reliability that advanced-node roadmaps demand.

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