Modern semiconductor manufacturing assumes that a clean silicon surface is “good enough” after standard HF-last processing.

In reality, this is not the case. After the HF-last clean, the silicon surface is briefly hydrogen-terminated. However, within minutes, it begins to regrow an ultra-thin, amorphous native oxide layer. At the same time, contaminants such as carbon and hydrogen remain and reattach to the interface.

This oxide layer is only a few angstroms thick, and contaminants are atomically small. But their impact is anything but insignificant.

What Actually Breaks?

At the atomic level, this unintended oxide and residual contamination introduce:

  • Interface mid-gap trap states
  • Charge scattering centres
  • Structural disorder at the surface

To better understand how these effects propagate directly into device behaviour, let’s look at three examples from the field:

In Quantum Devices

  • Charge noise increases
  • Coherence time shortens
  • Device reproducibility degrades

The result: scaling beyond today’s qubit counts becomes fundamentally harder.

In Advanced Sensors

  • Dark current and power consumption rises
  • Signal-to-noise ratio drops
  • Sensitivity becomes inconsistent

The result: Device performance is harder to improve, keeping the average selling price lower.

In Advanced Integration / Process Stacks

  • Variability increases
  • Interface quality becomes less controllable
  • Process windows tighten

The result: The yield in the final devices stays limited, and final performance is sacrificed.

In simple terms:
Even when everything else in the process is optimized, the interface itself becomes the limiting factor.

Why HF-Last Is No Longer Enough

HF-last cleaning has been the industry standard because it removes oxide effectively at that moment in time.

The problem is what happens next:

  • Oxide regrows almost immediately when exposed to air or moisture
  • Surface quality becomes dependent on handling and timing
  • Process reproducibility degrades
  • The starting surface is rough and non-uniform

To compensate, fabs today:

  • Minimize air exposure
  • Use inert environments
  • Apply high-temperature bake steps

These are workarounds – not solutions.

The Core Insight

The industry does not have a reliable way to preserve a truly oxide-free, contamination-free crystalline silicon interface through to the next process step.

And this matters more now than ever.

Why This Becomes Critical Now

In previous technology generations, small interface imperfections were tolerable.

That is no longer the case.

As devices move toward:

  • Quantum computing
  • Advanced sensing
  • Highly integrated process stacks and advanced nodes

Every atomic defect begins to matter.

What used to be a second-order effect is now a first-order scaling limit.

What an Ideal Solution Looks Like

To remove this bottleneck, the industry needs:

  • Oxide-free silicon surfaces
  • Minimal carbon and hydrogen contamination
  • Preserved crystalline order
  • No exposure between process steps

Crucially: The surface must remain pristine until the next layer is formed.

This strongly points toward integrated, cluster-based processing, where wafers move between steps without breaking the vacuum.

A New Approach: Eliminating the Interface Problem at the Source

To address this, SisuSemi has developed an ALP-based surface preparation process that removes contamination and the SiO2 layer, designed to:

  • Preventing the native SiO₂ layer growth after cleaning
  • Reduce residual contamination at the interface
  • Enable direct transfer to downstream processing steps

This approach is particularly suited for cluster tool integration, where surface quality can be preserved end-to-end.

The Impact: Small Interface Change, Large Economic Effect

At first glance, improving an atomically thin interface layer may sound incremental.

In practice, it directly influences the parameters that determine whether a device works, scales, or ships at yield.

When interface defects and native oxide are reduced:

  • Fewer trap states → lower charge noise: More stable electrical behaviour over time
  • Cleaner surface → improved layer formation: Better uniformity in downstream processes (ALD, epitaxy, contacts)
  • Controlled interface → reduced variability: Tighter distribution across dies and wafers

What This Means at the Device Level

The following numbers are the best estimates as well as measurement results:

  • Yield increase: +2–10% absolute improvement in defect-limited processes (especially in early-stage or sensitive device architectures)
  • Performance improvement:
  • Variability reduction:

The key insight: Interface quality affects not just average performance, but the tails of the distribution. That’s where yield lives.

Economic Translation: Why This Matters in Euros (and in USDs)

In semiconductor manufacturing, small physical improvements scale directly into financial impact.

  • Per wafer impact: Even a single percentage point of yield improvement on advanced wafers translates into roughly €50 – €200 per wafer, depending on device type and value density. For a single production line, this compounds into €2+ millions per year in additional output or reduced scrap. Each percentage point of yield improvement would drive a similar economic benefit.
  • Process leverage effect: Because the interface sits early in the process flow,
    • improvements propagate through every subsequent step
    • amplifying total performance degradation
  • ASP shift: With components that perform better, the higher Average Selling Price can be met. As analysed for sensors, the ASP shift provides the more drastic economic gain compared to the yield gain.                                            

The Strategic Takeaway

Interface quality is one of the rare levers where a small physical improvement
can unlock disproportionate economic and system-level value.

And critically:

  • This value is realized without redesigning the device
  • Only by improving the starting surface condition

Why This Is a Strategic Inflection Point

At the core, this is more of a technology enabler, rather than process optimization.

If oxide-free interfaces can be reliably achieved:

  • Quantum devices can scale further and faster
  • Sensor performance can improve beyond current limits
  • Advanced integration becomes more predictable

The Bottom Line

Oxide-free interfaces are not a “nice-to-have.”
They are becoming a prerequisite for next-generation semiconductor performance.

And until today, they have remained unresolved.

What Happens Next

The industry is approaching a point where:

  • Traditional surface preparation is no longer sufficient
  • Interface control becomes a defining capability
  • Integrated processing architectures gain importance

The question is no longer: “Can we tolerate imperfect interfaces?”

But rather: “How much value are we leaving on the table by not fixing them?”

Closing Thought

The next leap in semiconductor performance comes from something fundamental: A surface that is finally as clean and as controlled as we think it is.

Contact us to learn more