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How atomic-level impurities hinder analogue IC performance and reliability

Overcoming Atomic-Level Defects in GAA Designs: Challenges and Opportunities for the Semiconductor Industry

As the semiconductor industry marches toward ever-smaller nodes and higher performance targets, Gate-All-Around (GAA) transistors have emerged as a promising architecture for pushing Moore’s Law
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Case Study: Enhancing Chip Yield and Assembly Efficiency Through Advanced Surface Passivation

A global leader in radiation detection and safety faced critical efficiency and yield challenges during the assembly and testing phase of their neutron detector sensor
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Interface-Defect Density Kills Chip Performance

Defects have been one of the biggest issues for the semiconductor industry since its day one causing yield loss, reliability issues, and performance bottlenecks.   As logic and memory nodes shrink,
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How atomic-level cleaning technologies help meet challenges in medical ICs

In medical integrated circuits (ICs), ensuring the highest quality and performance is critical. Medical ICs are used in a variety of sensitive applications, including diagnostic
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Why Semiconductor R&D Teams Must Consider Atomic-Level Defects and Contamination in Chip Design

In the race to develop faster, smaller and more energy-efficient chips, design teams often focus intensely on architecture, functionality and scaling strategies. However, an often-underappreciated
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How Atomic-Level Surface Defects and Contamination Drive Up Water Consumption in Semiconductor Fabrication

Turning OSAT Challenges into Opportunities: How Sidewall Passivation Can Drive Yield and Market Advantage 

Outsourced Semiconductor Assembly and Test (OSAT) providers operate in one of the most competitive segments of the semiconductor value chain. Margins are thin, customer expectations
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AI at the Edge: Why Power Consumption Becomes Mission Critical

AI at the Edge: Why Power Consumption Becomes Mission Critical

Edge devices — from smartphones to IoT sensors, wearables and remote embedded systems — are increasingly expected to run AI inference locally. The benefits are
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How Atomic-Level Surface Defects and Contamination Drive Up Water Consumption in Semiconductor Fabrication

How Atomic-Level Surface Defects and Contamination Drive Up Water Consumption in Semiconductor Fabrication

Atomic-level defects and contamination in semiconductor surfaces affect on the water consumption in semiconductor fabrication. Impurities have a significant impact on manufactured chip performance and
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Researcher conducting semiconductor interface analysis aimed at reducing defect density and improving device yield.

Atomic-Level Impurities in Semiconductor Interfaces: A Strategic Guide for Business Development Teams

In today’s advanced semiconductor manufacturing, reducing defect density defines the difference between average and world-class yield performance. SisuSemi’s atomic-level approach helps to eliminate microscopic impurities
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Building stakeholder confidence with feasibility testing

Meeting the energy challenge: Smarter IoT, edge AI and mobile devices with SisuSemi

We are witnessing an unprecedented surge in connected devices. With nearly 20 billion IoT nodes already deployed—and close to 20 billion mobile devices in use—the
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