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Building stakeholder confidence with feasibility testing

How SisuSemi enables ex-situ workflows earlier considered impossible with atomic-level cleanliness

Background – Why Q-time matters In semiconductor manufacturing, even a short delay between processing steps can degrade the wafer surface. This “queue time” (Q‑time) is
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The Multi-Million Euro “Dirt” Problem: Why Atomic-Level Purity is the New Business Critical for GAA

In the race toward sub-3nm nodes, Gate-All-Around (GAA) is the undeniable future. It offers superior electrostatic control and the scalability required to keep Moore’s Law
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RCA Cleaning: Challenges at the Atomic Scale in Semiconductor Fabrication and How SisuSemi's Ultra-High-Vacuum Technology Can Help

The Hidden Cost of Complacency: Why Semiconductor Companies Can’t Afford to Ignore Atomic-Level Defects

As semiconductor nodes shrink past 3nm and the industry races toward angstrom-scale manufacturing, a troubling pattern has emerged: many companies continue treating atomic-level defects and
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Next-Gen Atomic-level Cleaning for state-of-the-art semiconductors and sub 20nm technology

Bridging Design and Manufacturing: Tackling Atomic-Level Defects for Better Chips

In the semiconductor industry, the pressure to deliver faster, more reliable and more energy-efficient devices grows with every process node. At 5nm, 3nm and soon
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How atomic-level impurities hinder analogue IC performance and reliability

Overcoming Atomic-Level Defects in GAA Designs: Challenges and Opportunities for the Semiconductor Industry

As the semiconductor industry marches toward ever-smaller nodes and higher performance targets, Gate-All-Around (GAA) transistors have emerged as a promising architecture for pushing Moore’s Law
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Case Study: Enhancing Chip Yield and Assembly Efficiency Through Advanced Surface Passivation

A global leader in radiation detection and safety faced critical efficiency and yield challenges during the assembly and testing phase of their neutron detector sensor
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Interface-Defect Density Kills Chip Performance

Defects have been one of the biggest issues for the semiconductor industry since its day one causing yield loss, reliability issues, and performance bottlenecks.   As logic and memory nodes shrink,
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How atomic-level cleaning technologies help meet challenges in medical ICs

In medical integrated circuits (ICs), ensuring the highest quality and performance is critical. Medical ICs are used in a variety of sensitive applications, including diagnostic
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Why Semiconductor R&D Teams Must Consider Atomic-Level Defects and Contamination in Chip Design

In the race to develop faster, smaller and more energy-efficient chips, design teams often focus intensely on architecture, functionality and scaling strategies. However, an often-underappreciated
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How Atomic-Level Surface Defects and Contamination Drive Up Water Consumption in Semiconductor Fabrication

Turning OSAT Challenges into Opportunities: How Sidewall Passivation Can Drive Yield and Market Advantage 

Outsourced Semiconductor Assembly and Test (OSAT) providers operate in one of the most competitive segments of the semiconductor value chain. Margins are thin, customer expectations
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